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| 型號： | IT80C52XXX-16SHXXX |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 23/81頁 |
| 文件大小： | 663K |
| 代理商： | IT80C52XXX-16SHXXX |
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3
ATtiny28L/V
1062F–AVR–07/06
rupt on low-level input feature enables the ATtiny28 to be highly responsive to external
events, still featuring the lowest power consumption while in the power-down modes.
The device is manufactured using Atmel’s high-density, nonvolatile memory technology.
By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel
ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective
solution to many embedded control applications. The ATtiny28 AVR is supported with a
full suite of program and system development tools including: macro assemblers, pro-
gram debugger/simulators, in-circuit emulators and evaluation kits.
Pin Descriptions
VCC
Supply voltage pin.
GND
Ground pin.
Port A (PA3..PA0)
Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED
driver. At V
CC = 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are
bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Port B (PB7..PB0)
Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B
pins that are externally pulled low will source current if the pull-ups are activated.
Port B also serves the functions of various special features of the ATtiny28 as listed on
page 27. If any of the special features are enabled, the pull-up(s) on the corresponding
pin(s) is automatically disabled. The port pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port D (PD7..PD0)
Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for
each bit). The port pins are tri-stated when a reset condition becomes active, even if the
clock is not running.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
Figure 2.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IT80F | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|50V V(DRM)|8A I(T)RMS|TO-220 |
| IT80G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRIAC|50V V(DRM)|8A I(T)RMS|TO-220 |
| IT810B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| IT8152FG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Specification|Errata_v0.1 for it8152fg_v0.3.4 |
| IT8172G | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RISC Companion Chip|Errata v0.2 for it8172g_v0.6 |
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