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| 型號(hào)： | IT80C52CXXX-L16:RD |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 7/324頁(yè) |
| 文件大?。?/td> | 3748K |
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104
2513L–AVR–03/2013
ATmega162/V
Timer/Counter0,
Timer/Counter1,
and
Timer/Counter3
Prescalers
Timer/Counter3, Timer/Counter1, and Timer/Counter0 share the same prescaler module, but
the Timer/Counters can have different prescaler settings. The description below applies to
Timer/Counter3, Timer/Counter1, and Timer/Counter0.
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
CLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either f
CLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or
f
CLK_I/O/1024. In addition, Timer/Counter3 has the option of choosing fCLK_I/O/16 and fCLK_I/O/32.
Prescaler Reset
The prescaler is free running, i.e., operates independently of the clock select logic of the
Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1, and Timer/Counter0. Since
the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of prescaling arti-
facts occurs when the Timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the Timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024,
additional selections for Timer/Counter3: 32 and 64).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it
is connected to.
External Clock Source
An external clock source applied to the Tn/T0 pin can be used as Timer/Counter clock
(clk
T1/clkT0) for Timer/Counter1 and Timer/Counter0. The Tn/T0 pin is sampled once every sys-
tem clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then
passed through the edge detector. Figure 44 shows a functional equivalent block diagram of the
Tn/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of
the internal system clock (clk
I/O). The latch is transparent in the high period of the internal system
clock.
The edge detector generates one clk
T1/clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 44. Tn/T0 Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn/T0 pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Tn_sync
(To Clock
Select Logic)
Edge Detector
Synchronization
DQ
LE
DQ
Tn
clk
I/O
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