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1
pac81_01
ispPAC81
In-System Programmable Analog Circuit
October 2001
Data Sheet
Features
■
In-System Programmable(ISP) Analog
Instrument Ampli
fi
er Gain Stage
Precision Active Filtering (10kHz to 75kHz)
Continuous-Time Fifth Order Low Pass Topology
Dual, A/B Con
fi
guration Memory
Non-Volatile E
2
CMOS
Cells
IEEE 1149.1 JTAG Serial Port Programming
■
Unique Flexibility and Performance
Programmable Gain Range (0dB to 20dB)
Implements Multiple Filter Types: Elliptical,
Chebyshev, Butterworth
Low Distortion (THD < -80dB at 10kHz)
Auto-Calibrated Input Offset Voltage
■
True Differential I/O
High CMR Instrument Ampli
fi
er Input
2.5V Common Mode Reference on Chip
Rail-to-Rail Voltage Outputs
■
Single Supply 5V Operation
Power Dissipation of 133mW
16-Pin Plastic SOIC, PDIP Packages
■
Applications Include Integrated
Single +5V Supply Signal Conditioning
Programmable Filters With Fully Differential I/O
Analog Front Ends, 12-Bit Data Acq. Systems
DSP System Front End Signal Conditioning
High-Performance Reconstruction Filters
Typical Application Diagram
Functional Block Diagram
Description
The ispPAC81 is a member of the Lattice family of In-System
Programmable analog circuits, digitally con
fi
gured via nonvol-
atile E
2
CMOS technology.
Analog building blocks, called PACell(s), replace traditional
analog components such as opamps, eliminating the need for
external resistors and capacitors. With no requirement for
external con
fi
guration components, ispPAC81 expedites the
design process, simplifying prototype circuit implementation
and change, while providing high-performance integrated
functionality. With all components on chip, there is no longer a
concern of performance degradation due to component mis-
match or other external factors. The ispPAC81 provides reli-
able and repeatable performance, every time.
Designers con
fi
gure the ispPAC81 and verify its performance
using PAC-Designer
, an easy-to-use, Microsoft Windows
compatible program. A
fi
lter con
fi
guration database is pro-
vided whereby thousands of different con
fi
gurations can be
realized. No special understanding of
fi
lter synthesis is
required beyond that of general speci
fi
cations such as corner
frequency and stopband attenuation, etc. The software lists
the possible choices that meet the designer’s speci
fi
cations
which can then be loaded directly into either of two device (A/
B) con
fi
gurations from the lookup table. Device programming
is supported using PC parallel port I/O operations.
The ispPAC81 is con
fi
gured through its IEEE Standard 1149.1
compliant serial port. The
fl
exible In-System Programming
capability enables programming, veri
fi
cation and recon
fi
gura-
tion, if desired, directly on the printed circuit board.
Vin
VREFout
A/B & Gain
SPI Control
Reference
Ain-
Ain+
12-Bit Differential
Input ADC
DSP
ispPAC81
5V
5V
5V
OUT+
OUT–
IN+
IN–
VS
VREFOUT
TEST
TEST
E2CMOS Cfg A
Ref & Auto-Cal
ISP Control
E2CMOS Cfg B
IA
OA
5th Order LPF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TDI
TDO
TCK
TMS
GND
CAL
ENSPI
CS
ispPAC81