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參數(shù)資料
| 型號： | ISPLSI2032-180LT48 |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | In-System Programmable High Density PLD |
| 中文描述： | EE PLD, 7.5 ns, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 153K |
| 代理商： | ISPLSI2032-180LT48 |
Specifications
ispLSI 2032/A
10
Power consumption in the ispLSI 2032 and 2032A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
60
80
100
1
20
40
60
80
100 120 140 160 180
f
max (MHz)
I
C
Notes: Configuration of Two 16-bit Counters
Typical Current at 5V, 25
°
C
ispLSI 2032/A (-150, -180)
ispLSI 2032/A (-80, -110, -135)
90
70
40
50
0127A/2032A
ICC can be estimated for the ispLSI 2032/A using the following equation:
For 2032/A -150, -180: ICC(mA) = 30 + (# of PTs * 0.46) + (# of nets * Max freq * 0.012)
For 2032/A -135, -110, -80: ICC(mA)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
= 21 + (# of PTs * 0.30) + (# of nets * Max freq * 0.012)
110
120
Power Consumption
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI2032-180LT48I | In-System Programmable High Density PLD |
| ISPLSI2032-80LJ | In-System Programmable High Density PLD |
| ISPLSI2032-80LJI | In-System Programmable High Density PLD |
| ISPLSI2032-80LT44 | In-System Programmable High Density PLD |
| ISPLSI2032-80LT44I | In-System Programmable High Density PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2032-180LT48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ispLSI2032-80LJ | 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ispLSI2032-80LJI | 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2032-80LT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ispLSI2032-80LT44 | 功能描述:CPLD - 復雜可編程邏輯器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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