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參數(shù)資料
| 型號(hào)： | ISPLSI 2064E-135LT100 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 1/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLD ISP 64I/O 7.2NS 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ispLSI® 2000E |
| 可編程類(lèi)型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 7.5ns |
| 電壓電源 - 內(nèi)部： | 4.75 V ~ 5.25 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 64 |
| 門(mén)數(shù)： | 2000 |
| 輸入/輸出數(shù)： | 64 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | ISPLSI2064E-135LT100 |
ispLSI
2064E
In-System Programmable
SuperFAST High Density PLD
2064e_06
1
Description
The ispLSI 2064E is a High Density Programmable Logic
Device. The device contains 64 Registers, 64 Universal
I/O pins, four Dedicated Input Pins, three Dedicated
Clock Input Pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2064E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2064E offers non-volatile reprogrammability of the logic,
as well as the interconnect to provide truly reconfigurable
systems.
The basic unit of logic on the ispLSI 2064E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. B7 (see Figure 1). There are a total of 16 GLBs in the
ispLSI 2064E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Copyright 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
January 2002
Features
SuperFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
— 100% Functionally and JEDEC Upward Compatible
with ispLSI 2064 Devices
HIGH PERFORMANCE E2CMOS TECHNOLOGY
—
fmax = 200 MHz Maximum Operating Frequency
—
tpd = 4.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
— ispJTAG In-System Programmable via IEEE 1149.1
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports Mixed
Voltage Systems
— PCI Compatible Outputs
— Open-Drain Output Option
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
Global Routing Pool
(GRP)
A0
A1
A3
Input
Bus
Output
Routing
Pool
(ORP)
B3
B2
B1
B0
Input
Bus
Output
Routing
Pool
(ORP)
A2
GLB
Logic
Array
DQ
A4
A5
A6
A7
Input Bus
Output Routing Pool (ORP)
B7
B6
B5
B4
Input Bus
Output Routing Pool (ORP)
0139/2064E
B7
B6
B5
B4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPLSI2064E-135LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064E-200LT | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI2064E-200LT100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類(lèi)型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI2064V | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
| ISPLSI2064V-100LJ44 | 制造商:LATTICE 制造商全稱(chēng):Lattice Semiconductor 功能描述:3.3V High Density Programmable Logic |
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