- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362815 > ISPGDX240VA-10B388I Telecomm/Datacomm PDF資料下載
參數(shù)資料
| 型號(hào)： | ISPGDX240VA-10B388I |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 1/23頁(yè) |
| 文件大小： | 226K |
| 代理商： | ISPGDX240VA-10B388I |
當(dāng)前第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)
1
ispGDX
In-System Programmable
3.3V Generic Digital Crosspoint
240VA
Functional Block Diagram
Features
IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL
CROSSPOINT FAMILY
— 240 I/O, “Any Input to Any Output” Routing
— Advanced Architecture Addresses Programmable
PCB Interconnect, Bus Interface Integration and
Jumper/Switch Replacement
— Fixed HIGH or LOW Output Option for Jumper/DIP
Switch Emulation
— Space-Saving Fine Pitch BGA Packaging
— Dedicated IEEE 1149.1-Compliant Boundary Scan
Test
HIGH PERFORMANCE E
2
CMOS
TECHNOLOGY
— 3.3V Core Power Supply
— 4.5ns Input-to-Output/4.0ns Clock-to-Output Delay
— 200MHz Maximum Clock Frequency
— TTL/3.3V/2.5V Compatible Input Thresholds and
Output Levels (Individually Programmable)
— Low-Power: 20.0mA Quiescent Icc
— 24mA I
OL
Drive with Programmable Slew Rate
Control Option
— PCI Compatible Drive Capability
— Schmitt Trigger Inputs for Noise Immunity
— Electrically Erasable and Reprogrammable
— Non-Volatile E
2
CMOS Technology
ispGDXVA OFFERS THE FOLLOWING ADVANTAGES
— 3.3V In-System Programmable Using Boundary Scan
Test Access Port (TAP)
— Change Interconnects in Seconds
FLEXIBLE ARCHITECTURE
— Combinatorial/Latched/Registered Inputs or Outputs
— Individual I/O Tri-state Control with Polarity Control
— Dedicated Clock/Clock Enable Input Pins (four) or
Programmable Clocks/Clock Enables from I/O Pins (60)
— Single Level 4:1 Dynamic Path Selection (Tpd = 4.5ns)
— Programmable Wide-MUX Cascade Feature
Supports up to 16:1 MUX
— Programmable Pull-ups, Bus Hold Latch and Open
Drain on I/O Pins
— Outputs Tri-state During Power-up (“Live Insertion”
Friendly)
Global Routing
Pool
(GRP)
I/O
Cells
I/O Pins B
Boundary
Scan
Control
I/O
Cells
ISP
Control
I
I
I/O Pins D
Description
The ispGDXVA architecture provides a family of fast,
flexible programmable devices to address a variety of
system-level digital signal routing and interface require-
ments including:
Multi-Port Multiprocessor Interfaces
Wide Data and Address Bus Multiplexing
(e.g. 16:1 High-Speed Bus MUX)
Programmable Control Signal Routing
(e.g. Interrupts, DMAREQs, etc.)
Board-Level PCB Signal Routing for Prototyping or
Programmable Bus Interfaces
The ispGDX240VA device features fast operation, with
input-to-output signal delays (Tpd) of 4.5ns and clock-to-
output delays of 4.0ns.
The architecture of the devices consists of a series of
programmable I/O cells interconnected by a Global Rout-
ing Pool (GRP). All I/O pin inputs enter the GRP directly
or are registered or latched so they can be routed to the
required I/O outputs. I/O pin inputs are defined as four
sets (A,B,C,D) which have access to the four MUX inputs
gdx240va_05
Copyright 2002 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein
are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
February 2002
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPLSI1032E100LJ | Electrically-Erasable Complex PLD |
| ISPLSI1032E100LT | Electrically-Erasable Complex PLD |
| ISPLSI1032E125LJ | Electrically-Erasable Complex PLD |
| ISPLSI1032E125LT | Electrically-Erasable Complex PLD |
| ISPLSI1032E70LJ | Electrically-Erasable Complex PLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPGDX240VA-10BN388I | 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDX240VA-4B388 | 功能描述:模擬和數(shù)字交叉點(diǎn) IC 3.3V 240 I/O RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDX240VA-4BN388 | 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDX240VA-7B388 | 功能描述:模擬和數(shù)字交叉點(diǎn) IC 3.3V 240 I/O RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
| ISPGDX240VA-7B388I | 功能描述:模擬和數(shù)字交叉點(diǎn) IC PROGRAMMABLE GEN DIG CROSSPOINT RoHS:否 制造商:Micrel 配置:2 x 2 封裝 / 箱體:MLF-16 數(shù)據(jù)速率:10.7 Gbps 輸入電平:CML, LVDS, LVPECL 輸出電平:CML 電源電壓-最大:3.6 V 電源電壓-最小:2.375 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 產(chǎn)品:Digital Crosspoint 封裝:Tube |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。