參數(shù)資料
型號: ISP2312
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 4/6頁
文件大?。?/td> 119K
代理商: ISP2312
4
ISP2300
83230-580-00 C
QLogic Corporation
Fibre Channel Interface
The ISP2300 provides onboard gigabit transceivers for
direct connection to the Fibre Channel ports on copper
media. A standard 10-bit interface is also provided to
connect to external transceivers, if desired.
Fibre Channel Protocol Manager
The ISP2300 FPM has the following features:
I
Support for one Fibre Channel port
I
Support for 1-gigabit and 2-gigabit serial interfaces
I
Full-duplex data transfer rate up to 400 Mbytes/sec
I
10-bit interface to external transceivers
I
Integrated frame buffer that supports up to a
2112-byte frame payload
I
8B/10B encoder and decoder with clock skew
management
I
Support for an external frame buffer
The FPM transmits and receives data at the full Fibre
Channel rate of 106.25 or 212.50 Mbytes/sec. The on-chip
frame buffer includes separate areas for received data and
transmit data, as well as areas for managing special frames
such as command and response. The FPM receive path
validates and routes frames received from the Fibre
Channel to the appropriate area in the frame buffer.
The transmit path transmits frames from the frame buffer
to the Fibre Channel. The FPM automatically handles
frame delimiters and frame control.
The external buffer supports additional receive
buffering for 10-km optical Fibre Channel links to
eliminate dead time and allow a remote transmitter to send
frames continuously. Enough initial buffer credit can then
be issued by the ISP2300 to keep a remote transmitter busy
until one or more R_RDYs are received.
PCI Interface
The ISP2300 PCI interface has the following features:
I
33-MHz and 66-MHz 64-bit intelligent bus master
conventional PCI interface (PCI 2.2)
I
64-bit host memory addressing (dual-address cycle)
I
Five-channel DMA controller
I
32-bit PCI target mode for communication with the
host
I
Pipelined DMA registers for efficient scatter/gather
operations
I
32-bit DMA transfer counter for I/O transfer length
of up to four gigabytes
I
Support for PCI power management
I
Support for the
message signaled interrupt
function
I
Support for flash BIOS PROM
I
Support for subsystem ID
I
3.3-V and 5.0-V tolerant PCI I/O buffers
The ISP2300 is designed to interface directly to the PCI
bus and operate as a 64-bit DMA bus master. This function
is accomplished through a PCI bus interface unit (PBIU)
containing an onboard DMA controller. The PBIU
generates and samples PCI control signals, generates host
memory addresses, and facilitates the transfer of data
between host memory and the onboard frame buffer. It also
allows the host to access the ISP2300 internal registers and
communicate with the onboard RISC processor.
The ISP2300 supports the minimum power
management capabilities specified in revision 1.1 of the
PCI Bus Power Management Interface Specification
,
which defines power states D0-D3, where D0 provides
maximum power consumption and D3 provides minimal
power consumption. The D3 power state is entered by either
software (D3
hot
) or by physically removing power
(D3
cold
). Hot and cold refer to the presence or absence of
VCC, respectively.
The ISP2300 supports power states D0, D3 hot, and
D3 cold.
The ISP2300 onboard DMA controller consists of five
independent DMA channels that initiate transactions on the
PCI bus and transfer data between the host memory and
frame buffer. The command DMA channel is used mainly
by the RISC processor for small transfers. The two data
DMA channels, one to transmit and one to receive, transfer
data between the FC-AL and the PCI bus. The auto-DMA
request channel fetches commands from host memory over
the PCI bus. The auto-DMA response channel posts status
information to host memory.
The PBIU internally arbitrates between the five DMA
channels and alternately services them. Each DMA channel
has a set of DMA registers that are programmed for
transfers by the RISC processor.
RISC Processor
The ISP2300 RISC processor has the following
features:
I
Execution of multiple I/O control blocks from the
host memory
I
Reduced host intervention and interrupt overhead
I
One interrupt or less per I/O operation
One of the major features of the ISP2300 is its ability
to handle complete I/O transactions from start to finish with
no host intervention. This high level of integration is
accomplished with the onboard RISC processor.
The ISP2300 RISC processor controls the chip interfaces;
executes simultaneous, multiple IOCBs; and maintains the
required thread information for each transfer.
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