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參數(shù)資料
| 型號(hào)： | ISP2300 |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 119K |
| 代理商： | ISP2300 |
2
ISP2300
83230-580-00 C
QLogic Corporation
Subsystem Organization
To maximize I/O throughput and improve host and
Fibre Channel utilization, the ISP2300 incorporates a
high-speed, proprietary RISC processor; a Fibre Channel
protocol manager (FPM); integrated frame buffer memory;
and a host bus, five-channel, bus master DMA controller.
The FPM and host bus DMA controller operate
independently and concurrently under the control of the
onboard RISC processor for maximum system
performance.
The complete I/O subsystem solution using the
ISP2300 and directly connected hard drives is shown in
figure 2.
ADDRESS
Figure 1. ISP2300 Block Diagram
RECEIVE
FRAME BUFFER
TRANSMIT
PATH
CONTROL
REGISTERS
PCI INTERFACE
FRAME BUFFER
FIBRE ENGINE
REGISTER
FILE
ALU
ISP2300
DATA
PCI ADDRESS/DATA 64-BIT,
UP TO 66-MHz BUS
PCI
CONTROL
EXTERNAL
CODE/DATA
MEMORY
FLASH
BIOS
RECEIVE DATA
DMA CHANNEL
TRANSMIT
DATA DMA
CHANNEL
COMMAND
DMA
CHANNEL
MAILBOX
REGISTERS
CONTROL/
CONFIGURATION
REGISTERS
BOOT
CODE
MEM.
I/F
F
I
F
O
TRANSMIT
FRAME BUFFER
RSERIAL
GIGABIT
2
LOOP
IN
10
TEXT.
LOOP
IN
10
LOOP
OUT
TRSERIAL
GIGABIT
RECEIVE
PATH
LOOP
OUT
2
RISC
I/O BUS
SERIAL
EEPROM
FIBRE CHANNEL
RESPONSE
QUEUE
ISP2300
Figure 2. I/O Subsystem Design Using the ISP2300
PCI
INTERFACE
FIBRE
CHANNEL
INTERFACE
RISC
PCI
64
16
HOST
SOFTWARE
DRIVER
REQUEST
QUEUE
IOCBs
HOST MEMORY
P
C
I
B
U
S
EXTERNAL
CODE/DATA MEMORY
STORAGE AREA
NETWORK (SAN)
STORAGE SUBSYSTEM
SERVER
TAPE LIBRARY
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