參數(shù)資料
型號(hào)： ISP1520BD,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 31/54頁(yè)
文件大?。?/td> 288K
代理商： ISP1520BD,557
ISP1520_4
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2006
36 of 53
Philips Semiconductors
ISP1520
Hi-Speed USB hub controller
[1]
Excluding the rst transition from Idle state.
[2]
Characterized only, not tested. Limits guaranteed by design.
Table 43.
Dynamic characteristics: high-speed source electrical characteristics
VCC = 3.0 V to 3.6 V; Tamb = 40 °Cto+70 °C; test circuit Figure 21; unless otherwise specied.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tHSR
rise time
10 % to 90 %
500
-
ps
tHSF
fall time
90 % to 10 %
500
-
ps
Clock timing
tHSDRAT
high-speed data rate
479.76
-
480.24
Mbit/s
tHSFRAM
microframe interval
124.9375
-
125.0625
s
tHSRFI
consecutive microframe interval
difference
1
-
four high-speed
bit times
ns
Table 44.
Dynamic characteristics: full-speed source electrical characteristics
VCC = 3.0 V to 3.6 V; Tamb = 40 °Cto+70 °C; test circuit Figure 22; unless otherwise specied.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tFR
rise time
CL =50pF; 10%to90% of
|V
OH VOL|
4
-
20
ns
tFF
fall time
CL =50pF; 90%to10% of
|V
OH VOL|
4
-
20
ns
tFRFM
differential rise and fall time matching
-
111.1
%
VCRS
output signal crossover voltage
-
2.0
V
Data source timing[2]
tDJ1
source jitter total (including frequency
tolerance) to next transition
3.5
-
+3.5
ns
tDJ2
source jitter total (including frequency
tolerance) for paired transitions
4
-
+4
ns
tFEOPT
source SE0 interval of EOP
160
-
175
ns
tFDEOP
source jitter for differential transition to
SE0 transition
2
-
+5
ns
Receiver timing[2]
tJR1
receiver jitter to next transition
18.5
-
+18.5
ns
tJR2
receiver jitter for paired transitions
9
-
+9
ns
tFEOPR
receiver SE0 interval of EOP
accepted as EOP; see
82
-
ns
tFST
width of SE0 interval during differential
transition
rejected as EOP; see
--14
ns
Hub timing (downstream ports congured as full-speed)[2]
tFHDD
hub differential data delay (without cable) see Figure 14; CL = 0 pF
--44
ns
tFSOP
data bit width distortion after SOP
5
-
+5
ns
tFEOPD
hub EOP delay relative to tHDD
0
-
15
ns
tFHESK
hub EOP output width skew
15
-
+15
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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