參數(shù)資料
型號: ISP1181BBS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 20/70頁
文件大小: 341K
代理商: ISP1181BBS
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
20 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
11. Suspend and resume
11.1 Suspend conditions
The ISP1181B detects a USB suspend status when a constant idle state is present
on the USB bus for more than 3 ms.
The bus-powered devices that are suspended must not consume more than 500
μ
A
of current. This is achieved by shutting down power to system components or
supplying them with a reduced voltage.
The steps leading up to suspend status are as follows:
1. On detecting a wake-up-to-suspend transition, the ISP1181B sets bit SUSPND in
the Interrupt register. This will generate an interrupt if bit IESUSP in the Interrupt
Enable register is set.
2. When the firmware detects a suspend condition, it must prepare all system
components for the suspend state:
a. All signals connected to the ISP1181B must enter appropriate states to meet
the power consumption requirements of the suspend state.
b. All input pins of the ISP1181B must have a CMOS LOW or HIGH level.
3. In the interrupt service routine, the firmware must check the current status of the
USB bus. When bit BUSTATUS in the Interrupt register is logic 0, the USB bus
has left the suspend mode and the process must be aborted. Otherwise, the next
step can be executed.
4. To meet the suspend current requirements for a bus-powered device, the internal
clocks must be switched off by clearing bit CLKRUN in the Hardware
Configuration register.
5. When the firmware has set and cleared bit GOSUSP in the Mode register, the
ISP1181B enters the suspend state. In powered-off application, the ISP1181B
asserts output SUSPEND and switches off the internal clocks after 2 ms.
Figure 6
shows a typical timing diagram.
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