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| 型號： | ISP1161BD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Full-speed Universal Serial Bus single-chip host and device controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 92/127頁 |
| 文件大小： | 2762K |
| 代理商： | ISP1161BD |
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Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
92 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
Bit
Symbol
Reset
Access
7
6
5
4
3
2
1
0
DAKOLY
0
R/W
DRQPOL
1
R/W
DAKPOL
0
R/W
EOTPOL
0
R/W
WKUPCS
0
R/W
PWROFF
0
R/W
INTLVL
0
R/W
INTPOL
0
R/W
Table 82: Hardware Configuration Register: bit description
Bit
Symbol
Description
15
-
reserved
14
EXTPUL
A logic 1 indicates that an external 1.5 k
pull-up resistor is
used on pin D
+
and that SoftConnect is not used. Bus reset
value: unchanged.
13
NOLAZY
A logic 1 disables output on pin CLKOUT of the LazyClock
frequency (115 kHz
±
10 %) during ‘suspend’ state. A logic 0
causes pin CLKOUT to switch to LazyClock output after
approximately 2 ms delay, following the setting of bit GOSUSP
in the Mode Register. Bus reset value: unchanged.
12
CLKRUN
A logic 1 indicates that the internal clocks are always running,
even during ‘suspend’ state. A logic 0 switches off the internal
oscillator and PLL, when they are not needed. During ‘suspend’
state this bit must be made logic 0 to meet the suspend current
requirements. The clock is stopped after a delay of
approximately 2 ms, following the setting of bit GOSUSP in the
Mode Register. Bus reset value: unchanged.
11 to 8
CKDIV[3:0]
This field specifies the clock division factor N, which controls the
clock frequency on output CLKOUT. The output frequency in
MHz is given by 48 / (N + 1). The clock frequency range is
3 to 48 MHz (N = 0 to 15). with a reset value of 12 MHz (N = 3).
The hardware design guarantees no glitches during frequency
change. Bus reset value: unchanged.
7
DAKOLY
A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237
compatible DMA mode. Bus reset value: unchanged.
6
DRQPOL
Selects DREQ2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
5
DAKPOL
Selects DACK2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
4
EOTPOL
Selects EOT pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
3
WKUPCS
A logic 1 enables remote wake-up via a LOW level on input pin
CS. Bus reset value: unchanged.
2
PWROFF
A logic 1 enables powering-off during ‘suspend’ state. Output
D_SUSPEND pin is configured as a power switch control signal
for external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
1
INTLVL
Selects the interrupt signalling mode on output pin INT2
(0 = level, 1 = pulsed). In pulsed mode an interrupt produces an
166 ns pulse. See
Section 8.6.3
for details. Bus reset value:
unchanged.
0
INTPOL
Selects INT2 pin signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1161BM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus single-chip host and device controller |
| ISP1181 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device |
| ISP1181A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller |
| ISP1181ABS,518 | 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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