參數(shù)資料
型號(hào): ISP1161A1
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus single-chip host and device controller
中文描述: 通用串行總線的單芯片主機(jī)和設(shè)備控制器
文件頁數(shù): 45/127頁
文件大?。?/td> 2762K
代理商: ISP1161A1
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
45 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
[1]
[2]
[3]
IN: input for the USB host (ISP1161 transmits); OUT: output from the USB host (ISP1161 receives).
The data flow direction is determined by bit EPDIR in the Endpoint Configuration Register.
The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.
11.3.3
Endpoint FIFO size
The size of the FIFO determines the maximum packet size that the hardware can
support for a given endpoint. Only enabled endpoints are allocated space in the
shared FIFO storage, disabled endpoints have zero bytes.
Table 8
lists the
programmable FIFO sizes.
The following bits in the Endpoint Configuration Register (ECR) affect FIFO
allocation:
Endpoint enable bit (FIFOEN)
Size bits of an enabled endpoint (FFOSZ[3:0])
Isochronous bit of an enabled endpoint (FFOISO).
Remark:
Register changes that affect the allocation of the shared FIFO storage
among endpoints must
not
be made while valid data is present in any FIFO of the
enabled endpoints. Such changes will render
all
FIFO contents
undefined
.
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