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參數(shù)資料
| 型號(hào)： | ISP1048E |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | High-Density Programmable Logic |
| 中文描述： | 高密度可編程邏輯 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大?。?/td> | 158K |
| 代理商： | ISP1048E |
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Specifications
ispLSI 1048E
12
Maximum GRP Delay vs. GLB Loads
3
2
1
8
16
32
GLB Loads
G
1
4
5
6
7
4
0127A/1048E
8
48
ispLSI 1048E-50
ispLSI 1048E-70
ispLSI 1048E-90/100
ispLSI 1048E-125
9
10
ICC can be estimated for the ispLSI 1048E using the following equation:
ICC = 20 + (# of PTs * 0.42) + (# of nets * Max. freq * 0.010)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max. freq = Highest Clock Frequency to the device
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 4 GLB loads on
average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the
program in the device, the actual ICC should be verified.
0127B/1048E
Notes: Configuration of twelve 16-bit counters,
Typical current at 5V, 25
°
C
180
220
260
300
340
380
0
20
40
60
f
max (MHz)
80
100
120
140
I
C
ispLSI 1048E
Power Consumption
Power Consumption in the ispLSI 1048E device depends
on two primary factors: the speed at which the device is
operating and the number of Product Terms used. Figure
3 shows the relationship between power and operating
speed.
Figure 3. Typical Device Power Consumption vs fmax
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