13 FN7853.1 June 17, 2011 SPI INTERFACE (Notes 11, 12) SCLK Period tCLK Write Operation" />
參數(shù)資料
型號： ISLA222P20IRZ
廠商： Intersil
文件頁數(shù)： 5/33頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標準包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 830mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應商設備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
ISLA222P
13
FN7853.1
June 17, 2011
SPI INTERFACE (Notes 11, 12)
SCLK Period
tCLK
Write Operation
7
cycles
tCLK
Read Operation
16
cycles
CSB
↓ to SCLK↑ Setup Time
tS
Read or Write
28
cycles
CSB
↑ after SCLK↑ Hold Time
tH
Write
5
cycles
CSB
↑ after SCLK↓ Hold Time
tHR
Read
16
cycles
Data Valid to SCLK
↑ Setup Time
tDS
Write
6
cycles
Data Valid after SCLK
↑ Hold Time
tDH
Read or Write
4
cycles
Data Valid after SCLK
↓ Time
tDVR
Read
5
cycles
NOTES:
11. SPI Interface timing is directly proportional to the ADC sample period (tS). Values in Switching Specifications table reflect multiples of a 4ns sample
period, and must be scaled proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
Typical Performance Curves All typical performance characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN =-dBFS, fIN = 105MHz, fSAMPLE = 250MSPS.
FIGURE 3. SNR AND SFDR vs fIN
FIGURE 4. HD2 AND HD3 vs fIN
FIGURE 5. SNR AND SFDR vs AIN
FIGURE 6. HD2 AND HD3 vs AIN
60
65
70
75
80
85
90
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
S
N
R
(dBFS)
AND
S
F
DR
(dBc)
SNR AT 250MSPS
SFDR AT 250MSPS
SFDR AT 130MSPS
SNR AT 130MSPS
-105
-100
-95
-90
-85
-80
-75
-70
-65
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
HD2
A
ND
HD3
MA
GNITUDE
(dBc)
HD2 AT 250MSPS
HD3 AT 130MSPS
HD2 AT 130MSPS
HD3 AT 250MSPS
10
20
30
40
50
60
70
80
90
100
-60
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
SNR
AND
S
F
DR
SFDR (dBfs)
SFDR (dBc)
SNR (dBc)
SNR (dBfs)
-110
-100
-90
-80
-70
-60
-50
-40
-30
-60
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
HD3 (dBc)
HD2 (dBc)
HD2 (dBFS)
HD3 (dBFS)
HD2
A
ND
HD3
M
A
GNITUDE
(dBc)
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