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參數(shù)資料
| 型號： | ISL99203IIZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/16頁 |
| 文件大小： | 0K |
| 描述： | IC AMP AUDIO 5.5W MONO D 20WLCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | D 類 |
| 輸出類型： | 1-通道（單聲道），帶立體聲耳機(jī) |
| 在某負(fù)載時最大輸出功率 x 通道數(shù)量： | 1.5W x 1 @ 8 歐姆 |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 特點(diǎn)： | 消除爆音，差分輸入，I²C，靜音，短路和熱保護(hù)，關(guān)機(jī)，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 20-WLCSP |
| 封裝/外殼： | 20-UFBGA，WLCSP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL99203IIZ-TDKR |
ISL99203
14
FN7547.1
September 15, 2011
Theory of Operation
The ISL99203 supports an I2C bidirectional bus oriented
protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master always initiates data transfers and provides the
clock for both transmit and receive operations.
Therefore, the ISL99203 operates as a slave device in all
applications.
All communication over the I2C interface is conducted by
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 28). On power-up of the ISL99203, the SDA
pin is in the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The ISL99203 continuously monitors
the SDA and SCL lines for the START condition and does
not respond to any command until this condition is met
(see Figure 29). A START condition is ignored during the
power-up of the device.
All I2C interface operations must be terminated by a
STOP condition, which is a LOW to HIGH transition of
SDA while SCL is HIGH (see Figure 28). A STOP condition
at the end of a read operation, or at the end of a write
operation places the device in its standby mode.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting
device, either master or slave, releases the SDA bus
after transmitting eight bits. During the ninth clock cycle,
the receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data (see Figure 29).
The ISL99203 responds with an ACK after recognition of
a START condition followed by a valid Identification Byte,
and once again after successful receipt of an Address
Byte. The ISL99203 also responds with an ACK after
receiving a Data Byte of a write operation. The master
must respond with an ACK after receiving a Data Byte of
a read operation.
FIGURE 27. HEADPHONE OUTPUT - SHUTDOWN
Typical Performance Characteristics (Continued)
SDA
HEADPHONE OUTPUT
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
FIGURE 28. VALID DATA CHANGES, START, AND STOP CONDITIONS
ISL99203
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| ISL9K18120G3 | 功能描述:整流器 18A 1200V Stealth RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復(fù)時間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
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