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參數(shù)資料
| 型號： | ISL98002CRZ-140 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/28頁 |
| 文件大小： | 0K |
| 描述： | IC VID DIGITIZER 3CHN AFE 72-QFN |
| 標(biāo)準(zhǔn)包裝： | 840 |
| 位數(shù)： | 8 |
| 通道數(shù)： | 3 |
| 功率（瓦特）： | 525mW |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
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16
FN6535.1
December 7, 2009
Technical Highlights
The ISL98002 provides all the features of traditional triple
channel video AFEs, but adds several next-generation
enhancements, bringing performance and ease of use to
new levels.
DPLL
All video AFEs must phase lock to an HSYNC signal,
supplied either directly or embedded in the video stream
(Sync On Green). Historically, this has been implemented as
a traditional analog PLL. At SXGA and lower resolutions, an
analog PLL solution has proven adequate, if somewhat
troublesome (due to the need to adjust charge pump
currents, VCO ranges and other parameters to find the
optimum trade-off for a wide range of pixel rates).
As display resolutions and refresh rates have increased,
however, the pixel period has shrunk. An XGA pixel at a
60Hz refresh rate has 15.4ns to change and settle to its new
value. But at UXGA 75Hz, the pixel period is 4.9ns. Most
consumer graphics cards (even the ones with “350MHz”
DACs) spend most of that time slewing to the new pixel
value. The pixel may settle to its final value with 1ns or less
before it begins slewing to the next pixel. In many cases, it
rings and never settles at all. Thus precision, low-jitter
sampling is a fundamental requirement at these speeds, and
a difficult one for an analog PLL to meet.
The ISL98002's DPLL has less than 250ps of jitter,
peak-to-peak, and independent of the pixel rate. The DPLL
generates 64 phase steps per pixel (vs the industry standard
32), for fine, accurate positioning of the sampling point. The
crystal-locked NCO inside the DPLL completely eliminates
drift due to charge pump leakage, so there is inherently no
frequency or phase change across a line. An intelligent
all-digital loop filter/controller eliminates the need for the user
to have to program or change anything (except for the number
of pixels) to lock over a range from interlaced video (10MHz or
higher) to UXGA 60Hz (170MHz, with the ISL98002-170).
The DPLL eliminates much of the performance limitations and
complexity associated with noise-free digitization of high
speed signals.
Automatic Black Level Compensation (ABLC)
and Gain Control
Traditional video AFEs have an offset DAC prior to the ADC,
to both correct for offsets on the incoming video signals and
add/subtract an offset for user “brightness control” without
sacrificing the 8-bit dynamic range of the ADC. This solution
is adequate, but it places significant requirements on the
system's firmware, which must execute a loop that detects
the black portion of the signal and then serves the offset
DACs until that offset is nulled (or produces the desired ADC
output code). Once this has been accomplished, the offset
(both the offset in the AFE and the offset of the video card
generating the signal) is subject to drift (the temperature
inside a monitor or projector can easily change +50°C)
between power-on/offset calibration on a cold morning and
the temperature reached once the monitor and the monitor's
environment has reached a steady state. Offset can drift
significantly over +50°C, reducing image quality and
0x25
Sync Separator Control (0x00)
0
Three-state Sync
Outputs
0: VSYNCOUT, HSYNCOUT, HSOUT are active
(default)
1: VSYNCOUT, HSYNCOUT, HSOUT are in three-state
1
COAST Polarity
0: Coast active high (default)
1: Coast active low
Set to 0 for internal VSYNC extracted from CSYNC.
Set to 0 or 1 as appropriate to match external VSYNC
or external COAST.
2HSOUT Lock Edge
0: HSOUT's trailing edge is locked to selected
HSYNCIN's lock edge. Leading edge moves
backward in time as HSOUT width is increased
(X980xx default)
1: HSOUT's leading edge is locked to selected
HSYNCIN's lock edge. Trailing edge moves forward
in time as HSOUT width is increased
3
Reserved
Set to 0
4
VSYNCOUT Mode
0: VSYNCOUT is aligned to HSYNCOUT edge,
providing “perfect” VSYNC signal (default)
1: VSYNCOUT is “raw” integrator output
5
Reserved
Set to 0
6
Reserved
Set to 0
7
Reserved
Set to 0
Register Listing (Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
FUNCTION NAME
DESCRIPTION
ISL98002
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