參數(shù)資料
型號: ISL97651
廠商: Intersil Corporation
英文描述: 4-Channel Integrated LCD Supply
中文描述: 4通道集成LCD電源
文件頁數(shù): 17/19頁
文件大?。?/td> 307K
代理商: ISL97651
17
FN7493.2
March 15, 2007
A
VDD_delay
Generation Using DELB
DELB pin is an open drain internal N-FET output used to
drive an external optional P-FET to provide a delayed A
VDD
supply which also has no initial pedistal voltage (see
Figure 15 and compare the A
VDD
and A
VDD_delayed
curves). When the part is enabled, the N-FET is held off until
C
DLY
reaches the 4th peak in the start-up sequence. During
this period, the voltage potential of the source and gate of
the external P-FET (M0 in application diagram) should be
almost the same due to the presence of the resistor (R4)
across the source and gate, hence M0 will be off. Please
note that the maximum leakage of DELB in this period is
500nA. To avoid any mis-trigger, the maximum value of R4
should be less than:
Where V
GS(th)_min(M0)
is the minimum value of gate
threshold voltage of M0.
FIGURE 15. START-UP SEQUENCE
V
CDLY
EN
V
REF
V
BOOST
(A
VDD
)
V
LOGIC
V
OFF
DELAYED
V
BOOST
(A
VDD_delay
)
V
ON
A
V
V
O
,
V
O
S
F
C
NORMAL
OPERATION
FAULT
PRESENT
START-UP SEQUENCE
TIMED BY C
DLY
V
R
,
L
t
SS
t
START-UP
t
VOFF
V
IN
t
VON
t
VON-SLICE
V
ON SLICE
NOTE: Not to scale
R
4_max
V
-------------------------------------------
<
(EQ. 23)
ISL97651
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