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參數(shù)資料
| 型號： | ISL95811WFUZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/14頁 |
| 文件大小： | 0K |
| 描述： | IC POT 256TAPS 5BYTES 8-MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 10k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±45 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
11
FN6759.1
October 6, 2008
Protocol Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions (see
Figure 17). On power-up of the ISL95811, the SDA pin is in
the input mode.
All I2C interface operations must begin with a START
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL95811 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (see
Figure 17). A START condition is ignored during the
power-up sequence and during internal non-volatile write
cycles.
All I2C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH (see Figure 17). A STOP condition at the end
of a read operation, or at the end of a write operation to
volatile bytes only places the device in its standby mode. A
STOP condition during a write operation to a non-volatile
byte initiates an internal non-volatile write cycle. The device
enters its standby state when the internal non-volatile write
cycle is completed.
An ACK, Acknowledge, is a software convention used to
indicate a successful data transfer. The transmitting device,
either master or slave, releases the SDA bus after
transmitting 8 bits. During the ninth clock cycle, the receiver
pulls the SDA line LOW to acknowledge the reception of the
8 bits of data (see Figure 18).
The ISL95811 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL95811 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
A valid Identification Byte contains 0101000 as the seven
MSBs. The LSB is the Read/Write bit. Its value is “1” for a
Read operation and “0” for a Write operation (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
0
1
0
1000
R/W
(MSB)
(LSB)
FIGURE 17. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
ISL95811
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參數(shù)描述 |
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| ISL95811WFUZ-TK | 功能描述:IC POT 256TAPS 5BYTES 8-MSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:3,000 系列:DPP 接片:32 電阻（歐姆）:10k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 300 ppm/°C 存儲器類型:非易失 接口:3 線串行（芯片選擇，遞增，增/減） 電源電壓:2.5 V ~ 6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN（2x3） 包裝:帶卷 (TR) |
| ISL95812HRZ | 制造商:Intersil Corporation 功能描述:MULTI-PHASE VR12.5 SVD CORE CONTROLLER, 32LD 4X4 QFN - Rail/Tube 制造商:Intersil Corporation 功能描述:IC VOLT REG 1-3PHASES 32QFN |
| ISL95812HRZ-T | 制造商:Intersil Corporation 功能描述:MULTI-PHASE VR12.5 SVD CORE CONTROLLER, 32LD 4X4 QFN - Tape and Reel 制造商:Intersil Corporation 功能描述:IC VOLT REG 1-3PHASES 32QFN |
| ISL95812IRZ | 制造商:Intersil Corporation 功能描述:MULTI-PHASE VR12.5 SVD CORE CONTROLLER, 32LD 4X4 QFN - Rail/Tube 制造商:Intersil Corporation 功能描述:IC VOLT REG 1-3PHASES 32QFN |
| ISL95812IRZ-T | 制造商:Intersil Corporation 功能描述:MULTI-PHASE VR12.5 SVD CORE CONTROLLER, 32LD 4X4 QFN - Tape and Reel 制造商:Intersil Corporation 功能描述:IC VOLT REG 1-3PHASES 32QFN |
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