參數(shù)資料
型號(hào): ISL9305IRTHWLNCZ-T
廠商: Intersil
文件頁數(shù): 2/17頁
文件大?。?/td> 661K
描述: IC REG QD BUCK/LINEAR 16TQFN
產(chǎn)品培訓(xùn)模塊: Patient Monitoring and Diagnostic Equipment Solutions
標(biāo)準(zhǔn)包裝: 6,000
拓?fù)洌?/td> 降壓(降壓)(2),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 4
頻率 - 開關(guān): 3MHz
電壓/電流 - 輸出 1: 0.8 V ~ 5.5 V,800mA
電壓/電流 - 輸出 2: 0.8 V ~ 5.5 V,800mA
電壓/電流 - 輸出 3: 0.9 V ~ 3.3 V,350mA
帶 LED 驅(qū)動(dòng)器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 1.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-TQFN-EP(4x4)
包裝: 帶卷 (TR)
ISL9305H
2
FN7724.1
October 5, 2011
Pin Configuration
ISL9305H
(16 LD 4X4 TQFN)
TOP VIEW
TABLE 1. TYPICAL APPLICATION PARTS LIST
PARTS   DESCRIPTION    MANUFACTURER
PART NUMBER
SPECIFICATIONS
SIZE
L1, L2  Inductor
Sumida
CDRH2D14NP-1R5
1.5礖/1.80A/50m&  3.0mmx3.0mmx1.55mm
C1  Input capacitor   Murata
GRM21BR60J106KE19L   10礔/6.3V
0805
C2, C3 Intput capacitor   Murata
GRM185R60J105KE26D   1礔/6.3V
0603
C4, C5 Output capacitor  Murata
GRM21BR71A106KE51L   10礔/6.3V
0805
C6, C7 Output capacitor  Murata
GRM185R60J105KE26D   1礔/6.3V
0603
R1, R2,
R3, R4
Resistor
Various
1%, SMD, 0.1W
0603
E-PAD
1
2
3
4
5   6   7   8
9
10
11
12
13
14
15
16
SCLK
VINDCD1
DCDPG
FB2
VINDCD2
FB1
SDAT
GNDLDO
Pin Descriptions
PIN NUMBER
(TQFN)
NAME
DESCRIPTION
1
VINDCD1   Input voltage for buck converter DCD1 and it also serves as the power supply pin for the whole internal digital/analog
circuits.
2
FB1
Feedback pin for DCD1, connect external voltage divider resistors between DCDC1 output, this pin and ground. For
fixed output versions, connect this pin directly to the DCD1 output.
3
SCLK    I
2
C interface clock pin.
4
SDAT    I
2
C interface data pin.
5
VINLDO1   Input voltage for LDO1.
6
VOLDO1    Output voltage of LDO1.
7
VOLDO2    Output voltage of LDO2.
8
VINLDO2   Input voltage for LDO2.
9
GNDLDO   Power ground for LDO1 and LDO2.
10
DCDPG    The DCDPG pin is an open-drain output to indicate the state of the DCD1/DCD2 output voltages. When both DCD1
and DCD2 are enabled, the output is released to be pulled high by an external pull-up resistor if both converter
voltages are within the power good range. The pin will be pulled low if either DCD is outside their range. When only
one DCD is enabled, the state of the enabled DCDs output will define the state of the DCDPG pin. The DCDPG state
can be programmed for a delay of up to 200ms before being released to rise high. The programming range is
1ms~200ms through the I
2
C interface.
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