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參數(shù)資料
| 型號： | ISL88813IP846Z |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | UP Supervisor with Watchdog Timer,Power-Fail Comparator, Manual Reset and Adjustable Power-On Reset |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, DIP-8 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大?。?/td> | 518K |
| 代理商： | ISL88813IP846Z |
3
FN8092.0
October 18, 2005
Pin Descriptions
ISL88705,
ISL88706
ISL88716,
ISL88813
ISL88707,
ISL88708
NAME
DESCRIPTION
1
1
1
MR
Manual Reset Input.
A reset signal is generated when this input is pulled low.
The MR input
is an active low debounced input to which a user can connect a push-button to add manual
reset capability or drive with a signal. The MR pin has an internal 100k
pull-up.
2
2
2
V
DD
Power Supply Terminal.
The voltage at this pin is compared against an internal factory-
programmed voltage trip point, V
TH1
. A reset is first asserted when the device is initially
powered up to ensure that the power supply has stabilized. Thereafter, reset is again asserted
whenever V
DD
falls below V
TH1
. The device is designed with hysteresis to help prevent
chattering due to noise and is immune to brief power-supply transients. The voltage threshold
V
TH1
is specified in the part number suffix.
3
3
3
GND
Ground Connection
4
4
4
PFI
Power-Fail Input
This is an auxiliary monitored voltage input with a 1.25V threshold that
causes PFO state to follow the PFI input state.
5
5
5
PFO
Power-Fail Output.
This output goes high if the voltage on PFI is greater than 1.25V,
otherwise PFO stays low.
6
C
POR
Adjustable POR Time-out Delay Input.
Connecting an external capacitor from C
POR
to
ground allows the user to increase the Power On Reset timeout (t
POR
) from the nominal
200ms.
6
6
WDI
Watchdog Input.
The Watchdog Input takes an input from a microprocessor and ensures that
it periodically toggles the WDI pin, otherwise the internal nominal 1.6s watchdog timer runs out,
then reset is asserted and WDO is pulled low. The internal Watchdog Timer is cleared
whenever the WDI sees a rising or falling edge or the device is manually reset. Floating WDI
or connecting WDI to a high-impedance three-state buffer disables the watchdog feature.
7
7
RST
Active-Low Reset Output.
The RST output is an active low open drain output that is pulled
low to GND when reset is asserted. Reset is asserted whenever;
1. The device is first powered up,
2. V
DD
falls below its minimum voltage sense level or
3. MR is asserted.
The reset output continues to be asserted for typically 200ms after V
DD
rises above the reset
threshold or MR input goes from low to high. A watchdog time-out will not trigger a reset unless
WDO is connected to MR.
7
8
RST
Active-High Reset Output.
The RST pin functions identically to its complementary RST
output but is an active high push pull output. RST is set high to V
DD
when reset is asserted.
See the RST description for more details on conditions that cause a reset.
8
8
WDO
Watchdog Output
. This output is pulled low when the nominal 1.6s internal Watchdog Timer
expires and does not go high again until the watchdog is cleared. WDO also goes low during
low V
DD
conditions. Whenever V
DD
is below the reset threshold, WDO stays low. However,
unlike RESET, WDO does not have a minimum pulse width. As soon as V
DD
rises above the
reset threshold, WDO goes high with no delay.
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
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