參數(shù)資料
型號： ISL8723
廠商： Intersil Corporation
英文描述： Power Sequencing Controllers
中文描述： 電源順序控制器
文件頁數(shù)： 4/15頁
文件大?。?/td> 276K
代理商： ISL8723
4
FN6413.0
December 21, 2006
Absolute Maximum Ratings
Thermal Information
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V
DD
+6V
UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to V
DD
+0.3V
RESET#, DLY_ON, DLYOFF. . . . . . . . . . . . . . . -0.3V to V
DD
+0.3V
Operating Conditions
V
DD
Supply Voltage Range . . . . . . . . . . . . . . . . . . . .+2.5V to +5.0V
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Notes 1, 2)
4 x 4 QFN Package . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
θ
JA
(°C/W)
48
θ
JC
(°C/W)
9
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
3. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
V
DD
= 3.3V to +5V, T
A
= T
J
= -40°C to +85°C, Unless Otherwise Specified.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVLO
Undervoltage Lockout Falling Threshold
V
UVLOvth
T
A
= T
J
= +25°C
619
631
647
mV
Undervoltage Lockout Falling Threshold
V
UVLOvth
604
631
656
mV
Undervoltage Lockout Hysteresis
V
UVLOhys
-
9
-
mV
Undervoltage Lockout Threshold Range
RUVLOvth
Max V
UVLOvth
- Min V
UVLOvth
-
6
18
mV
Undervoltage Lockout Delay
TUVLOdel
ENABLE satisfied
-
10
-
ms
Transient Filter Duration
tFIL
V
DD
, UVLO, ENABLE glitch filter
-
7
-
μ
s
DELAY ON/OFF
Delay Charging Current
DLY_ichg
V
DLY
= 0V
0.9
1
1.115
μ
A
Delay Charging Current Range
DLY_ichg_r
DLY_ichg(max) - DLY_ichg(min)
-
0.01
0.05
μ
A
Delay Threshold Voltage
DLY_Vth
1.21
1.273
1.32
V
ENABLE/ENABLE#, RESET# AND SYSRST# I/O
ENABLE Threshold
V
ENh
Measured at V
DD
= 5V
-
1.28
1.35
V
ENABLE# Threshold
V
ENh
-
0.5 V
DD
-
V
ENABLE/ENABLE# Hysteresis
V
ENh -
V
ENl
Measured at V
DD
= 5V
-
0.1
0.2
V
ENABLE/ENABLE# Lockout Delay
TdelEN_LO
UVLO satisfied, EN to DLY_ON
-
10
-
ms
ENABLE/ENABLE# Input Capacitance
Cin_en
-
5
-
pF
RESET# Pull-up Voltage
Vpu_rst
-
V
DD
-
V
RESET# Pull-Down Current
I
RSTpd5
V
DD
= 5V, RST = 0.1V
-
13
-
mA
RESET# Delay after GATE High
T
RSTdel
GATE = V
DD
+5V
-
160
-
ms
RESET# Output Low
V
RSTl
Measured at V
DD
= 5V, 1mA
sourcing current
-
-
0.1
V
RESET Output Capacitance
Cout_rst
-
10
-
pF
SYSRST# Pull-up Voltage
Vpu_srst
-
V
DD
-0.5V
-
V
SYSRST# Pull-up Current
Ipu_srst
V
DD
= 3.3V, SYSRST# = 0.5V
-
12
-
μ
A
SYSRST# Pull Down Current
Ipu_5
V
DD
= 5V
-
2.7
-
μ
A
SYSRST# Low Output Voltage
Vol_srst
V
DD
= 5V, I
OUT
= 100
μ
A
-
0.1
V
ISL8723, ISL8724
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