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參數(shù)資料
| 型號： | DS1314 |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR NV W/BATT MON 3V 8-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 控制器類型： | 非易失性 RAM |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
DS1312
3 of 12
battery. Should BW not deactivate for this reason, the new battery can be detached for tBDBA and then re-
attached to clear BW .
NOTE: The DS1312 cannot constantly monitor an attached battery because such monitoring would
drastically reduce the life of the battery. As a result, the DS1312 only tests the battery for one second out
of every 24 hours and does not monitor the battery in any way between tests. If a good battery (one that
has not been previously flagged with BW ) is removed between battery tests, the DS1312 may not
immediately sense the removal and may not activate BW until the next scheduled battery test. If a battery
is then reattached to the DS1312, the battery may not be tested until the next scheduled test.
NOTE: Battery monitoring is only a useful technique when testing can be done regularly over the entire
life of a lithium battery. Because the DS1312 only performs battery monitoring when VCC is nominal,
systems which are powered-down for excessively long periods can completely drain their lithium cells
without receiving any advanced warning. To prevent such an occurrence, systems using the DS1312
battery monitoring feature should be powered–up periodically (at least once every few months) in order
to perform battery testing. Furthermore, anytime BW is activated on the first battery test after a power-up,
data integrity should be checked via checksum or other technique.
POWER MONITORING
DS1312S and DS1312E varieties have an additional reset pin. These varieties detect out-of-tolerance
power supply conditions and warn a processor-based system of impending power failure. When VCCI falls
below the trip point level defined by the TOL pin (VCCTP), the VCCI comparator activates the reset signal
RST
. Reset occurs in the range of 4.75 to 4.5 volts (5% tolerance) when the TOL pin is connected to
GND or in the range of 4.5 to 4.25 volts (10% tolerance) when TOL is connected to VCCO.
RST
also serves as a power-on reset during power-up. After VCCI exceeds VCCTP, RST will be held active
for 200 ms nominal (tRPU). This reset period is sufficiently long to prevent system operation during
power-on transients and to allow tREC to expire. RST has an open-drain output driver.
FRESHNESS SEAL MODE
When the battery is first attached to the DS1312 without VCC power applied, the device does not
immediately provide battery-backup power on VCCO. Only after VCCI exceeds VCCTP will the DS1312
leave Freshness Seal Mode. This mode allows a battery to be attached during manufacturing but not used
until after the system has been activated for the first time. As a result, no battery energy is drained during
storage and shipping.
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