參數(shù)資料
型號(hào)： ISL6537ACRZ
廠商： INTERSIL CORP
元件分類(lèi)： 穩(wěn)壓器
英文描述： PWM Control Circuit 16-PDIP -40 to 85
中文描述： 3.3 A DUAL SWITCHING CONTROLLER, 280 kHz SWITCHING FREQ-MAX, PQCC28
封裝： 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220VJJC, QFN-28
文件頁(yè)數(shù)： 11/15頁(yè)
文件大小： 488K
代理商： ISL6537ACRZ
5
FN9143.3
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537A enters a reduced
power mode and draws less than 1mA (ICC_S5) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1
F capacitor.
P12V (Pin 3)
The VTT regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6537A provide the return path
for the VTT LDO, and switching MOSFET gate drivers. High
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
VTT REGULATOR
Upper Divider Impedance
RU
-2.5
-
k
Lower Divider Impedance
RL
-2.5
-
k
VREF_OUT Buffer Source Current
IVREF_OUT
--
2
mA
Maximum VTT Load Current
IVTT_MAX
Periodic load applied with 30% duty cycle and
10ms period using ISL6537A_6506EVAL1
evaluation board (see Application Note AN1124)
-3
-
3
A
LINEAR REGULATORS
DC Gain
Guaranteed By Design
-
80
-
dB
Gain Bandwidth Product
GBWP
15
-
MHz
Slew Rate
SR
-
6
-
V/
s
DRIVEn High Output Voltage
DRIVEn Unloaded
9.75
10.0
-
V
DRIVEn Low Output Voltage
-0.16
0.50
V
DRIVEn High Output Source Current
VFB = 770mV, VDRIVEn = 0V
-
1.7
2.6
mA
DRIVEn Low Output Sink Current
VFB = 830mV, VDRIVEn = 10V
-
1.20
2.00
mA
VIDPGD
VTT_GMCH/CPU Rising Threshold
S0
.725
.740
-
V
VTT_GMCH/CPU Falling Threshold
S0
-
0.700 0.715
V
PROTECTION
OCSET Current Source
IOCSET
18
20
22
A
VTT_DDR Current Limit
By Design
-3.3
-
3.3
A
VDDQ OV Level
VFB/VREF
S0/S3
-
115
-
%
VDDQ UV Level
VFB/VREF
S0/S3
-
75
-
%
VTT_DDR OV Level
VTT/VVREF_IN S0
-
115
-
%
VTT_DDR UV Level
VTT/VVREF_IN S0
-
85
-
%
VGMCH UV Level
VFB4/VREF
S0
-
75
-
%
VTT_GMCH/CPU UV Level
VFB2/VREF
S0
-
75
-
%
Thermal Shutdown Limit
TSD
By Design
-
140
-
°C
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6537A
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