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參數(shù)資料
| 型號： | ISL6524 |
| 廠商： | Intersil Corporation |
| 英文描述： | Adjustable Precision Shunt Regulator 3-SOT-23 -40 to 85 |
| 中文描述： | VRM8.5 PWM和三線性電源系統(tǒng)控制器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 445K |
| 代理商： | ISL6524 |
8
FN9015.3
April 18, 2005
The T2 to T3 time interval is dependent upon the value of
C
SS13
. The same capacitor is also responsible for the ramp-
up time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommended in the circuit application
literature, consider the effects the different value will have on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.
Fault Protection
All four outputs are monitored and protected against extreme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.
An overvoltage on V
OUT1
output (VSEN1) disables outputs
1, 2, and 3, and latches the IC off. An undervoltage on
V
OUT4
output latches the IC off. A single overcurrent event
on output 1, or an undervoltage event on output 2 or 3,
increments the respective fault counters and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start re-
start. After three consecutive fault events on either counter,
the chip is latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also reset by
a successful start-up of all the outputs.
Figure 6 shows a simplified schematic of the fault logic. The
overcurrent latches are set dependent upon the states of the
overcurrent (OC1), output 2 and 3 undervoltage (UV2, UV3)
and the soft-start signals (SS13, SS24). Window
comparators monitor the SS pins and indicate when the
respective C
SS
pins are fully charged to above 4.0V (UP
signals). An undervoltage on either linear output (VSEN2,
VSEN3, or VSEN4) is ignored until the respective UP signal
goes high. This allows V
OUT3
and V
OUT4
to increase
without fault at start-up. Following an overcurrent event
(OC1, UV2, or UV3 event), bringing the SS24 pin below 0.8V
resets the overcurrent latch and generates a soft-started
ramp-up of the outputs 1, 2, and 3.
OUT1 Overvoltage Protection
The overvoltage circuit provides protection during the initial
application of power. For voltages on the VCC pin below the
power-on reset level (and above ~4V), the output level is
monitored for voltages above 1.3V. Should VSEN1 exceed
this level, the lower MOSFET, Q2, is driven on.
Overcurrent Protection
All outputs are protected against excessive overcurrents.
The PWM controller uses the upper MOSFET’s on-
resistance, r
DS(ON)
to monitor the current for protection
against a shorted output. All linear regulators monitor their
respective VSEN pins for undervoltage to protect against
excessive currents.
Figure 8 illustrates the overcurrent protection with an overload
on OUT1. The overload is applied at T0 and the current
increases through the inductor (L
OUT1
). At time T1, the OC1
comparator trips when the voltage across Q1 (i
D
r
DS(ON)
)
exceeds the level programmed by R
OCSET
. This inhibits
outputs 1, 2, and 3, discharges the soft-start capacitor C
SS24
with 28mA current sink, and increments the counter. Soft-start
capacitor C
SS13
is quickly discharged. C
SS13
starts ramping
up at T2 and initiates a new soft-start cycle. With OUT2 still
overloaded, the inductor current increases to trip the
overcurrent comparator. Again, this inhibits the outputs, but
the C
SS24
soft-start voltage continues increasing to above
FIGURE 6. SOFT-START INTERVAL
0V
10V
0V
TIME
PGOOD
SS13
V
OUT2
(1.2V)
V
OUT4
(1.8V)
T1
T2
T4
T0
T5
3.0V
V
OUT1
(1.65V)
V
OUT3
(1.5V)
VTTPG
SS24
ATX 3.3V
ATX 5V
ATX 12V
T3
FAULT
LATCH
S
R
Q
POR
COUNTER
OC1
UV4
UV2
UV3
4V
SS13
FAULT
R
FIGURE 7. FAULT LOGIC - SIMPLIFIED SCHEMATIC
SS13UP
OC
LATCH
INHIBIT1,2,3
S
R
Q
OV
4V
0.8V
SS24
SS24UP
Q
SSDOWN
COUNTER
>
S
R
Q
OC
LATCH
R
>
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