參數(shù)資料
型號(hào)： ISL6432CB-T
廠商： Intersil
文件頁(yè)數(shù)： 8/12頁(yè)
文件大?。?/td> 274K
描述： IC REG QD BCK/LINEAR 16-SOIC
標(biāo)準(zhǔn)包裝： 2,500
拓?fù)洌?/td> 降壓（降壓）同步（1），線(xiàn)性（LDO）（3）
功能： 任何功能
輸出數(shù)： 4
頻率 - 開(kāi)關(guān)： 300kHz
電壓/電流 - 輸出 1： 控制器
電壓/電流 - 輸出 2： 控制器
電壓/電流 - 輸出 3： 控制器
帶 LED 驅(qū)動(dòng)器： 無(wú)
帶監(jiān)控器： 無(wú)
帶序列發(fā)生器： 是
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： *
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： *
包裝： 帶卷 (TR)
8
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
IN
 at the
PHASE node. The PWM wave is smoothed by the output
filter (L
O
 and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter, with
a double pole break frequency at F
LC
 and a zero at F
ESR
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6432) and the impedance networks Z
IN
 
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with high 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
 and
180 degrees. The equations below relate the compensation
networks poles, zeros and gain to the components (R1, R2,
R3, C1, C2, and C3) in Figure 6. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filters Double Pole (~75% F
LC
)
3. Place 2
ND
 Zero at Filters Double Pole
4. Place 1
ST
 Pole at the ESR Zero
5. Place 2
ND
 Pole at Half the Switching Frequency
6. Check Gain against Error Amplifiers Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converters
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 6. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F
P2
 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 10 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
 and Z
IN
 to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
ACPI Implementation
The three linear controllers included within the ISL6432 can
independently be shut down, in order to accommodate
Advanced Configuration and Power Interface (ACPI) power
management features.
To shut down any of the linears, one needs to pull and keep
high the respective FB pin above a typical threshold of 1.25V.
One way to achieve this task is by using a logic gate coupled
through a small-signal diode. The diode should be placed as
close to the FB pin as possible to minimize stray capacitance
to this pin. Upon turn-off of the pull-up device, the respective
output undergoes a soft-start cycle, bringing the output within
regulation limits. On the regulators implementing this feature,
the parallel combination of the feedback resistors has to be
sufficiently high to allow ease of driving from the external
device. Considering the other restriction applying to the upper
range of this resistor combination (see Output Voltage
Selection paragraph), it is recommended the values of the
feedback resistors on an ACPI-enabled linear regulator output
meet the following constraint:
To turn off the switching regulator, use an open-drain or
open-collector device capable of pulling the OCSET pin (with
the attached R
OCSET
pull-up) below 1.25V. To minimize the
possibility of OC trips at levels different than predicted, a
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
0.8V
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER1
(PARASITIC)
Z
FB
+
-
0.8V
R
S1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6432
Z
IN
COMP
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
Z
IN
R
P1
SYNC
+
+
F
LC
1
2?/DIV>
L
O
C
O
?/DIV>
?/DIV>
--------------------------------------- -
=
F
ESR
1
2?nbsp  ESR   C
O
?/DIV>
?/DIV>
---------------------------------------- -
=
F
Z1
1
2?nbsp  R
?nbsp  2   C1
?/DIV>
-----------------------------------
=
F
Z2
1
2?nbsp   R
S1
R3
+
(
)   C3
?/DIV>
?/DIV>
--------------------------------------------------------- -
=
F
P1
1
2?nbsp  R
2
C1   C2
?/DIV>
C1   C2
+
--------------------- -
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
------------------------------------------------------ -
=
F
P2
1
2?nbsp  R
?nbsp  3   C3
?/DIV>
-----------------------------------
=
2k&
R
S
R
P
?/DIV>
R
S
R
P
+
--------------------- -   5k&
<
<
ISL6432
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