參數資料
型號: ISL6295
廠商: Intersil Corporation
英文描述: Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-TSSOP -40 to 85
中文描述: 低電壓電量計
文件頁數: 23/25頁
文件大小: 387K
代理商: ISL6295
23
FN9074.0
October 25, 2005
Cal/Setup Mode AND Registers
Cal/Setup mode allows the pack designer to re-program the
default SMBus address and/or change the calibration
parameters programmed at the factory for bandgap, voltage
reference, and oscillators trim values.
Entering Cal/Setup requires the host to request three
consecutive and specific incorrect SMBus addresses with no
interruptions between requests. These addresses are:
After each address is sent, the ISL6295 will NACK the
address. Once the sequence is complete, the ISL6295 will
enter Cal/Setup mode and allow access to the test mode
registers located in memory bank 2.
To exit Cal/Setup mode, re-enter the same address
sequence or power down the device. The ISL6295 will
always power up with test mode disabled.
The following registers are only available in test mode.
Addr1
Addr2
Addr3
hex 50
hex 52
hex 74
SMBUS ADDRESS REGISTERS - SMBaddr
(Address 80 Hex/128 Decimal)
7
6
5
4
3
2
1
0
SMBadd
Reserved
SMBAdd
SMBus Address: Defines the SMBus address
for this device.
Reserved
Reserved bit
BAND-GAP TRIM REGISTER - VBGT
(Address 81 Hex/129 Decimal)
7
6
5
4
3
2
1
0
Reserved
Vbgt
Reserved
Reserved bits
Vbgt
Band-gap Voltage trim setting:
Nominal setting = 0111
LSB voltage step = 4mV
VOLTAGE REFERENCE TRIM REGISTER - VREFT
(Address 82Hex/130 Decimal)
7
6
5
4
3
2
1
0
GPIOen1
GPIOen0
Vreft
GPIOen1
‘ IO1 pin GPIO enable: Setting this bit to ‘1’ configures
the GPAD/IO1 pin to be used as a GPIO. When
enabled as GPIO, the GPAD accumulation function in
the ACCctrl register and the trip function in the TRIPctrl
register must be disabled.
GPIOen0
IO0 pin GPIO enable: Setting this bit to ‘1’ configures
the NTC pin to be used as a GPIO. When enabled as
GPIO, the external temperature accumulation function
in the ACCctrl register must be disabled.
Vreft
Voltage Reference trim setting:
Nominal setting = 011111
LSB voltage step = 0.2%
MAIN OSCILLATOR TRIM REGISTER - MOSCT
(Address 83 Hex/131 Decimal)
7
6
5
4
3
2
1
0
Reserved
MOsct
Reserved
Reserved bit. Must be set to ‘0’.
MOsct
Main Oscillator trim setting:
Nominal setting = 0111111
LSB frequency step = 0.25%
CLOCK TEST MODE REGISTER - clkTM
(Address 84 Hex/132 Decimal)
7
6
5
4
3
2
1
0
Revision
ExtClk
clkTM
Revision
This is a read-only register identifying the silicon
revision number of the device.
ExtClk
External Clock enable: When set, the clock input
to the accumulators and digital control logic within
the ISL6295 is taken from the NTC pin.
For production test only. Must be set to ‘0’ during
normal operation.
clkTM
Clock Test Mode control: These bits can be
used to speed up testing of the clock divider
chain used to generate the internal 2Hz
accumulator clock (Tacc). This test mode can
also be used to speed up the accumulator clock
for faster accumulator test time. During normal
operation, the 2Hz clock is derived by dividing
the main 131kHz reference clock through a
16-bit divider chain. The divider chain can be
bypassed as follows:
clkTM = 00: Normal operation (Tacc = 2Hz)
clkTM = 01: Use only divider bits 0-5
(Tacc = 2kHz)
clkTM = 10: Use only divider bits 6-11
(Tacc = 2kHz)
clkTM = 11: Use only divider bits 12-15
(Tacc = 8.2kHz)
For production test only. Must be set to ‘00’
during normal operation.
ISL6295
相關PDF資料
PDF描述
ISL6295CV Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-TSSOP -40 to 85
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