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參數(shù)資料
| 型號： | ISL59921IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANLG VID LINE TRPL 20-QFN |
| 標準包裝： | 72 |
| 類型： | 視頻延遲線 |
| 應用： | RGB 視頻信號 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VQFN 裸露焊盤 |
| 供應商設備封裝： | 20-QFN 裸露焊盤（5x5） |
| 包裝： | 管件 |
4
FN6826.2
August 31, 2010
POWER SUPPLY CHARACTERISTICS
V+
VSP, VSPO Positive Supply Range
+4.5
+5.5
V
V-
VSM, VSMO Negative Supply Range
-4.5
-5.5
V
ISP
Positive Supply Current (Note 3)
ISL59920
98
115
127
mA
ISL59921, ISL59922
98
125
146
mA
ISL59923
74
90
106
mA
ISPO
Positive Output Supply Current (Note 3)
ISL59920
11.3
13
15.3
mA
ISL59921, ISL59922
11.3
13
16.3
mA
ISL59923
9.9
13
16
mA
ISM
Negative Supply Current (Note 3)
-35.45
-31
-26
mA
ISMO
Negative Output Supply Current (Note 3)
ISL59920, ISL59921, ISL59922
-15.5
-13
-11
mA
ISL59923
-17.5
-13
-9.5
mA
ΔISP
Supply Current (Note 3)
Increase in ISP per unit step in delay per
channel
0.9
mA
ISTANDBY
Positive Supply Standby Current (Note 3)
Chip enable = 0V
2.6
mA
SERIAL INTERFACE CHARACTERISTICS
tMAX
Max SCLOCK Frequency
Maximum programming clock speed
10
MHz
tSEN_SETUP
SENABLE to SCLOCK falling edge setup time.
See Figure 33.
SENABLE falling edge should occur at least
tSEN_SETUP ns after previous (ignored) clock
and tSEN_SETUP before next (desired) clock.
Clock edges occurring within t_en_ck of the
SENABLE falling edge will have
indeterminate effect.
10
ns
tSEN_CYCLE
Minimum Separation Between SENABLE rising
edge and next SENABLE falling edge. See Figure 33.
If SENABLE is taken low less than 3s after it
was taken high, there is a small possibility that
an offset correction will not be initiated.
3s
NOTES:
2. The limits for the “Nominal Delay Increment” are derived by taking the limits for the “Maximum Delay” and dividing by the number of steps for the
device. For the ISL59920, ISL59921, and ISL59922 the number of steps is 31; for the ISL59923 the number of steps is 15.
3. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
4. Offset measurements are referred to 75
Ω load as shown in Figure 1.
Electrical Specifications
VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25°C, exposed die plate = -5V, x2 = 5V,
RLOAD = 150Ω on all video outputs, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX
UNIT
FIGURE 1. VOS MEASUREMENT CONDITIONS
x2 -
75
Ω
VOS
VIN
VOUT
75
Ω
ISL59920, ISL59921, ISL59922, ISL59923
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL59921IRZ-EVALZ | 制造商:Intersil Corporation 功能描述:ISL59921IRZ-EVALZ (PB-FREE ) EVALUATION BOARD - ROHS COMPLIA - Bulk |
| ISL59921IRZ-T7 | 功能描述:視頻 IC ISL95810W SINGLE 256 TAP I2C 10KOHM XDCP RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ISL59922 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Analog Video Delay Lines |
| ISL59922IRZ | 功能描述:視頻 IC ISL95871C INTEGRTD FET CO-PACK BATRY CH RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| ISL59922IRZ-EVALZ | 制造商:Intersil Corporation 功能描述:ISL59922IRZ-EVALZ (PB-FREE ) EVALUATION BOARD - ROHS COMPLIA - Bulk |
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