26 Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems " />
參數(shù)資料
型號: ISL59603IRZ-T7A
廠商: Intersil
文件頁數(shù): 19/28頁
文件大?。?/td> 0K
描述: IC VIDEO EQUALIZER 20-QFN
產(chǎn)品培訓(xùn)模塊: ISL5960x MegaQ Overview
標(biāo)準(zhǔn)包裝: 250
系列: MegaQ™
類型: 視頻均衡器
應(yīng)用: 安全系統(tǒng),視頻路由
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(4x4)
包裝: 帶卷 (TR)
ISL59601, ISL59602, ISL59603, ISL59604, ISL59605
26
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6739.2
September 5, 2012
For additional products, see www.intersil.com/product_tree
Bypassing and Layout
Considerations
MegaQ requires a dedicated ground plane in order to function
properly. For 2-layer boards, pour a quarter-inch ground plane
extending around the device on both the top and bottom layers.
Ensure that the ground plane on the bottom layer is a solid plane
with no traces cutting through it. Bypass capacitors must be
placed as close as possible to the device in order to ensure good
performance at longer lengths of equalization. Ensure that the
ground connections for the bypass capacitors connect directly to
the same uniform ground plane described previously.
General PowerPAD Design Considerations
The thermal pad must be connected to the ground plane for heat
dissipation. Figure 50 is an example of how to use vias to remove
heat from the IC.
The thermal pad is electrically connected to GND through the
high resistance IC substrate. We recommend you fill the thermal
pad area with vias. The via array should be centered in the
thermal pad and placed such that the center on center spacing is
3x the via radius. Vias should be small, but large enough to allow
solder wicking during reflow. Connect all vias to ground. It is
important the vias have a low thermal resistance for efficient
heat transfer. Do not use “thermal relief” patterns. It is important
to have a solid connection of the plated-through hole to each
plane.
Power Dissipation
The maximum power dissipation allowed in a package is
determined according to Equation 1:
Where:
TJMAX = Maximum junction temperature
TAMAX = Maximum ambient temperature
ΘJA = Thermal resistance of the package
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the load, or:
for sourcing use Equation 2:
for sinking use Equation 3:
Where:
VS = Supply voltage
ISMAX = Maximum quiescent supply current
VOUT = Maximum output voltage of the application
RLOAD = Load resistance tied to ground
ILOAD = Load current
FIGURE 50. PCB VIA PATTERN
PDMAX
TJMAX TAMAX
ΘJA
----------------------------------------
=
(EQ. 1)
PDMAX
VS ISMAX VS VOUT
()
+
×
VOUT
RL
-------------
×
=
(EQ. 2)
PDMAX
VS ISMAX VOUT VS
()
+
×
ILOAD
×
=
(EQ. 3)
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