10 FN7451.3 August 16, 2012 Application Information General The ISL59444 is a 4:1 mux that is ideal as a matrix element in high perfor" />
參數(shù)資料
型號: ISL59444IBZ
廠商: Intersil
文件頁數(shù): 2/12頁
文件大小: 0K
描述: IC CROSSPOINT SW 1GHZ 4X1 16SOIC
標(biāo)準(zhǔn)包裝: 47
應(yīng)用: 4:1 多路復(fù)用器-放大器
電路數(shù): 1
-3db帶寬: 1GHz
轉(zhuǎn)換速率: 1515 V/µs
電流 - 電源: 18mA
電流 - 輸出 / 通道: 180mA
電壓 - 電源,單路/雙路(±): ±4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
產(chǎn)品目錄頁面: 1235 (CN2011-ZH PDF)
ISL59444
10
FN7451.3
August 16, 2012
Application Information
General
The ISL59444 is a 4:1 mux that is ideal as a matrix element in
high performance switchers and routers. The ISL59444 is
optimized to drive a 2pF in parallel with a 500 load. The
capacitance can be split between the PCB capacitance an and
external load capacitance. Their low input capacitance and high
input resistance provide excellent 50 or 75 terminations.
Capacitance at the Output
The output amplifier is optimized for capacitance to ground (CL)
directly on the output pin. Increased capacitance causes higher
peaking with an increase in bandwidth. The optimum range for
most applications is ~1.0pF to ~6pF. The optimum value can be
achieved through a combination of PC board trace capacitance
(CT) and an external capacitor (COUT). A good method to maintain
control over the output pin capacitance is to minimize the trace
length (CT) to the next component, and include a discrete surface
mount capacitor (COUT) directly at the output pin.
For large signal applications where overshoot is important the
circuit in Figure 24B should be used. The series resistor (RS) and
capacitor (CL) form a low pass network that limits system
bandwidth and reduces overshoot. The component values shown
result in a typical pulse response shown in Figure 20.
Ground Connections
For the best isolation and crosstalk rejection, the GND pin and
NIC pins must connect to the GND plane. The NIC pins are placed
on both sides of the input pins. These pins are not internally
connected to the die. It is recommended this pin be tied to
ground to minimize crosstalk.
Control Signals
S0, S1, HIZ - These pins are, TTL/CMOS compatible control
inputs. The S0, S1 pins select which one of the inputs connect to
the output. The HIZ pin is used to three-state the output
amplifiers. For control signal rise and fall times less than 10ns
the use of termination resistors close to the part will minimize
transients coupled to the output.
HIZ State
An internal pull-down resistor connected to the HIZ pin ensures
the device will be active with no connection to the HIZ pin. The
HIZ state is established within approximately 30ns by placing a
logic high (>2V) on the HIZ pin. If the HIZ state is selected, the
output is a high impedance 1.4M. Use this state to control the
logic when more than one mux shares a common output.
In the HIZ state the output is three-stated, and maintains its high
Z even in the presence of high slew rates. The supply current
during this state is basically the same as the active state.
Latch State
The latched control signals allow for synchronized channel switching.
When LE1 is low the master control latch loads the next switching
address (S0, S1), while the closed (assuming LE2 is the inverse of
LE1) slave control latch maintains the current state. LE2 switching
low closes the master latch (with previous assumption), loads the
now open slave latch, and switches the crosspoint to the newly
selected channel. Channel selection is asynchronous (changes with
any control signal change) if both LE1 and LE2 are low.
Application Circuits
FIGURE 24A. SMALL SIGNAL 200mVP-P APPLICATION CIRCUIT
FIGURE 24B. LARGE SIGNAL 1VP-P APPLICATION CIRCUIT
VIN
50
-
+
*CL: TOTAL LOAD CAPACITANCE
COUT: OUTPUT CAPACITANCE
CT: TRACE CAPACITANCE
COUT
RL = 500
VOUT
0pF
*CL = CT + COUT
CT
1.6pF
VIN
50
RL = 500
-
+
VOUT
1.6pF
22pF
25
CT
COUT
CL = CT + COUT
RS
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