theoretically improving the even order harmonic rejection, but likely reducing the signal swing available due to the output voltage compliance " />
參數資料
型號: ISL5727INZ
廠商: Intersil
文件頁數: 4/13頁
文件大小: 0K
描述: IC DAC DUAL 10BIT 3.3V 48-LQFP
標準包裝: 250
位數: 10
數據接口: 并聯
轉換器數目: 2
電壓電源: 模擬和數字
功率耗散(最大): 275 mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-TQFP(7x7)
包裝: 托盤
輸出數目和類型: 4 電流,單極
采樣率(每秒): *
12
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
RDIFF
ISL5727
RLOAD
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
OUTA
OUTB
VOUT = (2 x OUTA x REQ)V
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
1:1
REQ = 0.5 x (RLOAD//RDIFF)
AT EACH OUTPUT
FIGURE 14. ALTERNATIVE OUTPUT LOADING
ISL5727
OUTA
OUTB
VOUT = (2 x OUTA x REQ)V
REQ = 0.5 x (RLOAD//RDIFF//RA), WHERE RA = RB
AT EACH OUTPUT
RLOAD
RDIFF
RA
RB
LOAD SEEN BY THE TRANSFORMER
RLOAD REPRESENTS THE
Timing Diagram
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
IOUT
50%
tPW1
tPW2
tSU
tHLD
tSU
tPD
tHLD
D9-D0
W0
W1
W2
W3
OUTPUT = W0
OUTPUT = W1
tPD
OUTPUT = W-1
ISL5727
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