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| 型號： | ISL55211IRTZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP DIFF LOW NOISE 16TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Test and Measurement Equipment |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 5600 V/µs |
| -3db帶寬： | 1.6GHz |
| 電流 - 輸入偏壓： | 50µA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 35mA |
| 電流 - 輸出 / 通道： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 4.2 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-TQFN（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL55211IRTZ-T7ADKR |
ISL55211
17
FN7868.0
June 21, 2011
Layout Considerations
The ISL55211 pinout is organized to isolate signal I/O along one
axis of the package with ground, power and control pins on the
other axis. Ground and power should be planes coming into the
upper and lower sides of the package (see “Pin Configuration” on
page 2). The signal I/O should be laid out as tight as possible.
The ground pins and package backside metal contact should be
connected into a good ground plane. The power supply should
have both a large values electrolytic cap to ground, then a high
frequency ferrite beads, then 0.01F SMD ceramic caps at the
supply pins. Some improvement in HD2 performance may be
experienced by placing and X2Y cap between the two Vs+ pins
and ground underneath the package on the board back side. This
is 3 terminal device that is included in the Evaluation board
layout.
Evaluation Board (Rev. C)
Test circuit 1 (Figure 29) is implemented on an Evaluation Board
available from Intersil. This board includes a number of optional
features that not populated as the board is delivered. The full
Evaluation circuit is shown in Figure 40 where unloaded
(optional) elements are shown in green.
The nominal supply voltage for the board and device is a single
3.3V supply. From this, the ISL55210, ISL55211 generates an
internal common mode voltage of approximately 1.2V. That
voltage can be overridden by populating the two resistors and
potentiometer shown as R19 to R21 above.
The primary test purpose for this board is to implement different
interstage differential passive filters intended for the ADC
interface along with the ADC input impedances. The board is
delivered with only the output R's loaded to give a 200
Ω
differential load. This is done using the two 85
Ω resistors as R9
and R10, then the 4 0Ω elements (R10, R12, R24, and R25) and
finally the two shunt elements R13 and R14 set to 35.5Ω.
Including the 50
Ω measurement load on the output side of the
1:1 transformer reflecting in parallel with the two 35 resistors
takes the nominal AC shunt impedance to 71
Ω||50Ω = 29.3Ω.
This adds to the two 85
Ω series output elements to give a total
load across the amplifier outputs of 170
Ω + 29.3Ω = 199.3Ω.
To test a particular ADC interface RLC filter and converter input
impedance, replace R11 and R12 with RF chip inductors, load
C10 and C11 with the specified ADC input capacitance and R26
with the specified ADC differential input R. With these loaded,
the remaining resistive elements (R24, R25, R13, R14) are set to
hit a desired total parallel impedance to implement the desired
filter (must be < than the ADC input differential R since that sits
in parallel with any "external" elements) and achieve a 250
Ω
source looking into each side of the tap point transformer.
This Evaluation board includes a user's manual showing a
number of example circuits and tested results and is available on
the Intersil web site on the ISL55211 Product Information Page.
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