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參數(shù)資料
| 型號： | ISL55141IVZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/14頁 |
| 文件大小： | 0K |
| 描述： | IC COMP CMOS HS 18V 14-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 窗口 |
| 元件數(shù)： | 1 |
| 電壓 - 電源，單路/雙路(±)： | 10 V ~ 18 V |
| 電壓 - 輸入偏移（最小值）： | 50mV @ -3V，12V |
| 電流 - 輸入偏壓（最小值）： | 0.025µA @ -3V，12V |
| 電流 - 靜態(tài)（最大值）： | 12.5mA |
| 傳輸延遲（最大）： | 15ns |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
6
FN6230.3
April 4, 2013
Application Information
The ISL55141, ISL55142, ISL55143 provide 1, 2 and 4 dual
threshold, three-state window comparator(s) in TSSOP or
QFN footprints. They offer a combination of speed (10ns Tpd
and wide voltage range (18V). This product directly
addresses the need for unique common-mode
characteristics while supplying a power-down feature.
points for an example propagation delay measurement.
Typical room temperature results are displayed in Figure 11.
is increased in the horizontal axis from 50mV above and
below the reference (1.5V) up to 2.5V above and below the
1.5V reference.
Two lines are displayed in Figure 11. One represents the
rising-to-rising delay (tPDLH) and the other the
falling-to-falling delay (tPDHL).
Comparator Features
These three-state window comparators feature high output
current capability, and user defined high and low output levels
to interface with a wide variety of logic families. Each receiver
comprises two comparators and each comparator has an
independent threshold level input, making it easy to
implement (Minimum1-VIH)/(Maximum 0-VIL) logic level
comparator functions. The CVAX and CVBX pins set the
threshold levels of the A and B comparators respectively. VOH
and VOL set all the comparator output levels, and VOH must
be more positive than VOL. These two inputs are unbuffered
supply pins, so the sources driving these pins must provide
adequate current for the expected load. VOH and VOL
typically connect to the power supplies of the logic device
driven by the comparator outputs.
The truth table for the receivers is given in Table 1. Receiver
outputs are not tri-statable, and do not incorporate any on-chip
short circuit current protection. Momentary short circuits to
GND, or any supply voltage, will not cause permanent
damage, but care must be taken to avoid longer duration short
circuits. If tolerable to the application, current limiting resistors
can be inserted in series with the QAX and QBX outputs to
protect the receiver outputs from damage due to overcurrent
conditions.
Power-down Features
The ISL55141, ISL55142, ISL55143 PD pin provides a
means of reducing current consumption when the device is
not in use. Supply currents fall from ~7mA to less than 10A
in the power-down mode. The device requires approximately
10s to power-down and 15s to power-up.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VEE pin is
connected to ground, one 0.1F ceramic capacitor should be
placed from the VCC pin to ground. A 4.7F tantalum
capacitor should then be connected from the VCC pin to
ground. This same capacitor combination should be placed
at each supply pin to ground if split supplies are to be used.
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver
level amplitudes are key in determining power supply
requirements as well as dissipation/cooling necessities.
Driver output patterns also impact these needs. The faster
the pin activity, the greater the need to supply current and
remove heat.
FIGURE 3. tPD RECEIVER SWITCHING TEST CIRCUIT
FIGURE 4. tPD RECEIVER PROPAGATION DELAY
MEASUREMENT POINTS
Test Circuits and Waveforms (Continued)
+
-
+
-
VINP
QA
QB
+11 VCC
-3 VEE
CVA 1.5V
CVB 1.5V
+5V-VOH
VOL
QX
50mV
-50mV
tPDLH
VOH (≈5V)
VOL (≈0V)
50%
tPDHL
VINP
1.5V
CVA = CVB = 1.5V
ISL55141, ISL55142, ISL55143
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參數(shù)描述 |
|---|---|
| ISL55142 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Speed 18V CMOS Comparators |
| ISL55142IRZ | 功能描述:IC COMP CMOS HS 18V 20-QFN RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ISL55142IRZ-T | 功能描述:IC COMP CMOS HS 18V 20-QFN RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ISL55142IVZ | 功能描述:IC COMP CMOS HS 18V 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標(biāo)準(zhǔn)）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
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