6 FN6550.3 May 6, 2013 Electrical Specifications - 1.8V Supply Test Conditions: V+ =" />
參數(shù)資料
型號(hào): ISL54501IHZ-T
廠商: Intersil
文件頁數(shù): 10/13頁
文件大?。?/td> 0K
描述: IC SWITCH SPDT SOT23-6
標(biāo)準(zhǔn)包裝: 3,000
功能: 開關(guān)
電路: 1 x SPST- NO
導(dǎo)通狀態(tài)電阻: 5 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5.5 V
電流 - 電源: 20nA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-23-6
包裝: 帶卷 (TR)
ISL54501, ISL54502
6
FN6550.3
May 6, 2013
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Note 10),
Unless Otherwise Specified. Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 11, 12)
TYP
MAX
(Notes 11, 12)
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range,
VANALOG
Full
0
-
V+
V
ON-Resistance, rON
V+ = 1.8V, ICOM = 10mA, VNO or VNC = 0V to V+
(Note 14, see Figure 4)
25
-
11.9
12.8
Ω
Full
-
13.8
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL =50Ω, CL = 35pF
(see Figure 1, Note 14)
25
-
70
-
ns
Full
-
130
-
ns
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL =50Ω, CL = 35pF
(see Figure 1, Note 14)
25
-
52
-
ns
Full
-
100
-
ns
Charge Injection, Q
VG = V+/2, RG = 0Ω, CL = 1.0nF (see Figure 2)
25
-
5.8
-
pC
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Full
-
0.4
V
Input Voltage High, VINH
Full
1-
-
V
NOTES:
10. VIN = input voltage to perform proper function.
11. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
13. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
14. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the opposite logic
sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
50%
tr < 20ns
tf < 20ns
tOFF
90%
V+
0V
VNO
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
V
OUT
V
(NO or NC)
R
L
R
L
r
ON
()
+
----------------------------
=
SWITCH
INPUT
LOGIC
INPUT
VOUT
RL
CL
COM
NO or NC
IN
50
Ω
35pF
GND
V+
C
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