6
FN6819.1
February 4, 2010
Input Voltage High, VSELH, VOEH
VDD = 4.3V to 5.5V
Full
2.0
-
-
V
Input Current, ISELL, IOEL
VDD = 5.5V, SEL = 0V, OE = 0V
Full
-
3.3
-
nA
Input Current, ISELH
VDD = 5.5V, SEL = 5.5V
Full
-
-3.6
-
nA
Input Current, IOEH
VDD = 5.5V, OE = 5.5V
Full
-
-8.2
-
nA
NOTES:
11. VLOGIC = Input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data
sheet.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with
lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-.
16. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
Electrical Specifications - 2.7V to 5.5V Supply
Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH =1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified.
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 12, 13) TYP
MAX
(Notes 12, 13) UNITS
50%
tr < 20ns
tf < 20ns
tOFF
90%
VDD
0V
VINPUT
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
V
OUT
V
(INPUT)
R
L
R
L
r
ON
+
------------------------
=
SWITCH
INPUT
VIN
VOUT
RL
CL
Dx
HSDxx
SEL
50
Ω
10pF
GND
VDD
C
OE
VINPUT
ISL54220