參數(shù)資料
型號: ISL54103IHZ-T7A
廠商: Intersil
文件頁數(shù): 4/8頁
文件大小: 0K
描述: IC ACCELERATOR DDCA DUAL SOT23-5
標(biāo)準(zhǔn)包裝: 1
類型: 纜線,DDCA
端子數(shù): 2
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SC-74A,SOT-753
供應(yīng)商設(shè)備封裝: SOT-23-5
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ISL54103IHZ-T7ADKR
4
FN6303.2
October 14, 2011
Absolute Maximum Ratings
Thermal Information
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 6.5V
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
ESD Min Other Pins (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV
ESD DDC1 and DDC2 Pins (HBM) . . . . . . . . . . . . . . . . . . . . . .>8kV
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Electrical Specifications
Over all operating conditions unless otherwise specified, Typical values are measured at VDD = 3.3V and
TA = +25°C
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNIT
ANALOG PARAMETERS
VDD
Supply Voltage Range
2.7
5.5
V
VDD RAMP VDD Ramp Rate
0.05
50
V/ms
IDD
Supply Current
DDC1 = DDC2 = Open
80
100
A
IOUT_SB
Standby Pull-Up Current
DDC1 = DDC2 = VDD - 1.0V
80
125
A
IOUT_A1
Active Pull-Up Current
DDC1 = GND; DDC2 = Open
125
275
350
A
IOUT_A2
DDC1 = Open; DDC2 = GND
125
275
350
A
IOUT_B1
Boost Pull-Up Current (Figure 2) VTRIPL < DDC1 < VTRIPH, DDC2 = Open
1.6
2.2
mA
IOUT_B2
VTRIPL < DDC2 < VTRIPH, DDC1 = Open
1.6
2.2
mA
VTRIPL
Input Voltage Threshold Low
0.65
0.75
0.85
V
VTRIPH
Input Voltage Threshold High
VDD - 0.60
VDD - 0.50
VDD - 0.40
V
fMAX
DDC Max Frequency
100
kHz
NSS
Noise Spike Suppression
(Note 5) (Figure 10)
20
V-ns
NOTES:
5. Measured as area under triangular waveform above VTRIPL, with time as base and VIN as height (See Figure 10).
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
ISL54103
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