FN6579.2 March 11, 2011 Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, V" />
參數(shù)資料
型號(hào)： ISL54059EVAL1Z
廠商： Intersil
文件頁數(shù)： 11/14頁
文件大?。?/td> 0K
描述： EVALUATION BOARD FOR ISL54059
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，2:1 多路復(fù)用器
嵌入式： 否
已用 IC / 零件： ISL54059
主要屬性： 2 x SPDT 模擬開關(guān)
次要屬性： 1.8 V ~ 6.5 V 電源
已供物品： 板
6
FN6579.2
March 11, 2011
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.0V, VINL = 0.4V (Note 9), Unless Otherwise
Specified
.
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 10, 11) TYP
MAX
(Notes 10, 11) UNITS
ANALOG SWITCH CHARACTERISTICS
ON-Resistance, rON
V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)
to V+, (see Figure 5)
25
-
1.87
-
Ω
Full
-
1.97
-
Ω
rON Matching Between
Channels,
ΔrON
V+ = 1.8V, ICOM = 100mA, VNO or VNC = Voltage at
max rON (Note 13)
25
-
16
-
m
Ω
Full
-
30
-
m
Ω
rON Flatness, RFLAT(ON)
V+ = 1.8V, ICOM = 100mA, VNO or VNC = (V+ - 6.5V)
to V+ (Notes 12)
25
-
1.34
-
Ω
Full
-
1.43
-
Ω
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF
(see Figure 1)
25
-
145
-
ns
Full
-
150
-
ns
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF
(see Figure 1)
25
-
20
-
ns
Full
-
22
-
ns
Break-Before-Make Time Delay,
tD
V+ = 1.8V, VNO or VNC = 1.8V, RL = 50Ω, CL = 35pF
(see Figure 3)
Full
-
130
-
ns
Charge Injection, Q
CL = 1.0nF, VG = 0V, RG = 0Ω (see Figure 2)
25
-
40
-
pC
NOx or NCx OFF Capacitance,
COFF
f = 1MHz (see Figure 7)
25
-
36
-
pF
COMx ON Capacitance,
CCOM(ON)
f = 1MHz (see Figure 7)
25
-
88
-
pF
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
25
-
0.4
V
Input Voltage High, VINH
25
1.0
-
V
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
25
-0.5
-
0.5
A
Input Current, IINH, IINL
V+ = 2.0V, VIN = 0V or V+
Full
-
0.19
-
A
NOTES:
9. VIN = input voltage to perform proper function.
10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
12. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON
value, between NC1 and NC2 or between NO1 and NO2.
14. Limits established by characterization and are not production tested.
ISL54059
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