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參數(shù)資料
| 型號： | ISL45042IR-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/9頁 |
| 文件大小： | 0K |
| 描述： | IC LCD MODULE CALIBRATOR 8-DFN |
| 標準包裝： | 6,000 |
| 類型： | 校準器 |
| 應(yīng)用： | LCD 顯示器 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
2
FN6072.9
April 13, 2011
Pin Descriptions
PIN
FUNCTION
OUT
Adjustable Sink Current Output Pin. The current sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink
current divided by 128. See SET pin function in “Pin Descriptions” on page 2 for the maximum adjustable sink current setting.
AVDD
High-Voltage Analog Supply. Connects to top of external resistor divider to determine the VCOM voltage. 10.8V to 20V for EEPROM
programming, 4.5V to 20V normal operation (before/after programming). Bypass to GND with 0.1F de-coupling capacitor.
DNC
Do Not Connect. This pin may be left unconnected or tied to GND. Do not apply any non-zero voltages or signals to this pin.
GND
Ground connection.
VDD
Low-Voltage Digital Supply for digital logic. Typically 3V to 3.6V. Bypass to GND with 0.1F de-coupling capacitor.
CTL
Internal Counter Up/Down Control and Internal EEPROM Programming Control Input. If CE is high, a mid-to-low transition increments
the 7-bit counter, raising the DAC setting, increasing the OUT sink current, and lowering the divider voltage at OUT. A mid-to-high
transition decrements the 7-bit counter, lowering the DAC setting, decreasing the OUT sink current, and increasing the divider voltage
at OUT. Applying 4.9V and above with appropriately arranged timing will overwrite EEPROM with the contents in the 7-bit counter.
See EEPROM Programming section in “Electrical Specifications” table on page 4 for details.
CE
Counter Enable Pin with internal pull-down resistor. Connect CE to VDD to enable adjustment of the output sink current. Float or
connect CE to GND to prevent further adjustment or programming.
SET
Maximum Sink Current Adjustment Point. Connect a resistor from the SET pin to GND to set the maximum adjustable sink current of
the OUT pin. The maximum adjustable sink current is equal to (AVDD/20) divided by RSET.
Block Diagram
ISL45042
DIGITAL INTERFACE
WITH THRESHOLD
SENSORS
UP/DOWN COUNTER
WITH PRESET
LATCHES
EEPROM
OR
NVL MEMORY
ANALOG DCP AND
CURRENT OUTPUT
BLOCK
AVDD
IOUT
SET
CTL
CE
VDD
GND
UP
DWN
PWRUP
PRGM
POR
PRGM
IBIAS
READ
PRGM MEMORY
400k
Ω
to
5M
Ω
ISL45042
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