參數(shù)資料
型號(hào): ISL43410IUZ-T
廠商: Intersil
文件頁(yè)數(shù): 12/13頁(yè)
文件大?。?/td> 0K
描述: IC SWITCH DPDT 10MSOP
標(biāo)準(zhǔn)包裝: 2,500
功能: 開(kāi)關(guān)
電路: 1 x DPDT
導(dǎo)通狀態(tài)電阻: 50 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2 V ~ 12 V
電流 - 電源: 100pA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
8
FN6044.4
May 12, 2008
Detailed Descriptions
The ISL43410 operates from a single 2V to 12V supply with
low ON-resistance (115
Ω) and high speed operation
(tON = 60ns, tOFF = 30ns). The ISL43410 is especially well
suited to portable battery powered equipment thanks to the
low operating supply voltage (2.0V), low power consumption
(3W), low leakage currents (5nA max), and the tiny MSOP
and QFN packaging. High frequency applications also benefit
from the wide bandwidth, and the very high OFF-isolation
(75dB) and crosstalk rejection (-85dB).
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1k
Ω
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not applicable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch, so two small signal
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above GND. The low leakage current performance is
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
FIGURE 4. OFF-ISOLATION TEST CIRCUIT
FIGURE 5. rON TEST CIRCUIT
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Test Circuits and Waveforms (Continued)
ANALYZER
RL
SIGNAL
GENERATOR
V+
C
0V OR V+
NO OR NC
COM
ADD
GND
INH
0V OR V+
V+
C
0V OR V+
NO OR NC
COM
ADD
GND
VNX
V1
rON = V1/1mA
1mA
INH
0V OR V+
ANALYZER
V+
C
NO1 OR NC1
SIGNAL
GENERATOR
RL
GND
ADD
COM1
50
Ω
NC
COM2
NO2 OR NC2
INH
V+
C
GND
NO OR NC
COM
ADD
IMPEDANCE
ANALYZER
0V OR V+
INH
ISL43410
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