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參數(shù)資料
| 型號： | ISL4270EIRZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XMITTER/RCVR ESD RS232 32-QFN |
| 標準包裝： | 1 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN 裸露焊盤（5x5） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1241 (CN2011-ZH PDF) |
| 其它名稱： | ISL4270EIRZ-TDKR |
7
FN6041.2
June 16, 2010
mode an RC time constant after this rising edge. The time
constant isn’t critical, because the ISL4270E remains
powered up for 30 seconds after the FORCEON falling edge,
even if there are no signal transitions. This gives slow-to-
wake systems (e.g., a mouse) plenty of time to start
transmitting, and as long as it starts transmitting within 30
seconds both systems remain enabled.
VL Logic Supply Input
Unlike other RS-232 interface devices where the CMOS
outputs swing between 0 and VCC, the ISL4270E features a
separate logic supply input (VL; 1.8V to 5V, regardless of
VCC) that sets VOH for the receiver and INVALID outputs.
Connecting VL to a host logic supply lower than VCC,
prevents the ISL4270E outputs from forward biasing the
input diodes of a logic device powered by that lower supply.
Connecting VL to a logic supply greater than VCC ensures
that the receiver and INVALID output levels are compatible
even with the CMOS input VIH of AC, HC, and CD4000
devices. Note that the VL supply current increases to 100μA
powers the transmitter and logic inputs, thereby setting their
switching thresholds to levels compatible with the logic
supply. This separate logic supply pin allows a great deal of
flexibility in interfacing to systems with different logic
supplies. If logic translation isn’t required, connect VL to the
ISL4270E VCC.
TABLE 2. POWERDOWN LOGIC TRUTH TABLE
RCVR OR XMTR
EDGE WITHIN 30
SEC?
FORCEOFF
INPUT
FORCEON
INPUT
TRANSMITTER
OUTPUTS
RECEIVER
OUTPUTS
RS-232 LEVEL
PRESENT AT
RECEIVER INPUT?
INVALID
OUTPUT
MODE OF OPERATION
NO
H
Active
NO
L
Normal Operation (Enhanced
Auto Powerdown Disabled)
NO
H
Active
YES
H
YES
H
L
Active
NO
L
Normal Operation (Enhanced
Auto Powerdown Enabled)
YES
H
L
Active
YES
H
NO
H
L
High-Z
Active
NO
L
Powerdown Due to Enhanced
Auto Powerdown Logic
NO
H
L
High-Z
Active
YES
H
X
L
X
High-Z
Active
NO
L
Manual Powerdown
X
L
X
High-Z
Active
YES
H
INVALID DRIVING FORCEON AND FORCEOFF (EMULATES AUTOMATIC POWERDOWN)
X
NOTE 5
Active
YES
H
Normal Operation
X
NOTE 5
High-Z
Active
NO
L
Forced Auto Powerdown
NOTES:
5. Input is connected to INVALID Output.
FIGURE 2. CONNECTIONS FOR MANUAL POWERDOWN
PWR
FORCEOFF, FORCEON
CPU
I/O
ISL4270E
MGT
LOGIC
UART
VL
I/O CHIP
POWER SUPPLY
VCC
INVALID
FIGURE 3. CIRCUIT TO ENSURE IMMEDIATE POWER UP
WHEN EXITING FORCED POWERDOWN
FORCEOFF
FORCEON
POWER
MASTER POWERDOWN LINE
1M
Ω
0.1
μF
MANAGEMENT
UNIT
ISL4270E
ISL4270E
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