參數(shù)資料
型號: ISL4223EIRZ-T7A
廠商: Intersil
文件頁數(shù): 3/14頁
文件大?。?/td> 0K
描述: IC TXRX RS232 ESD 20QFN
標準包裝: 250
類型: 收發(fā)器
驅動器/接收器數(shù): 2/2
規(guī)程: RS232
電源電壓: 2.7 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 20-VQFN 裸露焊盤
供應商設備封裝: 20-QFN 裸露焊盤(5x5)
包裝: 帶卷 (TR)
11
FN6045.6
May 13, 2010
Interconnection with 3V and 5V Logic
The ISL4221E, ISL4223E and ISL3232E directly interface
with 5V CMOS and TTL logic families. Nevertheless, with the
ISL4221E, ISL4223E and ISL3232E at 3.3V, and the logic
supply at 5V, AC, HC, and CD4000 outputs can properly
drive ISL4221E, ISL4223E and ISL3232E inputs, but
ISL4221E, ISL4223E and ISL3232E outputs do not reach
the minimum VIH for these logic families. See Table 3 for
more information.
±15kV ESD Protection
All pins on ISL4221E, ISL4223E and ISL3232E devices
include ESD protection structures, but the RS-232 pins
(transmitter outputs and receiver inputs) incorporate
advanced structures, which allow them to survive ESD
events up to ±15kV. The RS-232 pins are particularly
vulnerable to ESD damage because they typically connect to
an exposed port on the exterior of the finished product.
Simply touching the port pins, or connecting a cable, can
cause an ESD event that might destroy unprotected ICs.
These new ESD structures protect the device whether or not
it is powered-up, protect without allowing any latchup
mechanism to activate, and don’t interfere with RS-232
signals as large as ±25V.
Human Body Model (HBM) Testing
As the name implies, this test method emulates the ESD
event delivered to an IC during human handling. The tester
delivers the charge through a 1.5k
Ω current limiting resistor,
making the test less severe than the IEC61000 test which
utilizes a 330
Ω limiting resistor. The HBM method
determines an ICs ability to withstand the ESD transients
typically present during handling and manufacturing. Due to
the random nature of these events, each pin is tested with
respect to all other pins. The RS-232 pins on “E” family
devices can withstand HBM ESD events to
±15kV.
IEC61000-4-2 Testing
The IEC61000-4-2 test method applies to finished
equipment, rather than to an individual IC. Therefore, the
pins most likely to suffer an ESD event are those that are
exposed to the outside world (the RS-232 pins in this case),
and the IC is tested in its typical application configuration
(power applied) rather than testing each pin-to-pin
combination. The lower current limiting resistor coupled with
the larger charge storage capacitor yields a test that is much
more severe than the HBM test. The extra ESD protection
built into this device’s RS-232 pins allows the design of
equipment meeting level 4 criteria without the need for
additional board level protection on the RS-232 port.
AIR-GAP DISCHARGE TEST METHOD
For this test method, a charged probe tip moves toward the
IC pin until the voltage arcs to it. The current waveform
delivered to the IC pin depends on approach speed,
humidity, temperature, etc., so it is difficult to obtain
repeatable results. The “E” device RS-232 pins withstand
±15kV air-gap discharges.
CONTACT DISCHARGE TEST METHOD
During the contact discharge test, the probe contacts the
tested pin before the probe tip is energized, thereby
eliminating the variables associated with the air-gap
discharge. The result is a more repeatable and predictable
test, but equipment limits prevent testing devices at voltages
higher than ±8kV. All “E” family devices survive ±8kV contact
discharges on the RS-232 pins.
TABLE 3. LOGIC FAMILY COMPATIBILITY WITH VARIOUS
SUPPLY VOLTAGES
SYSTEM
POWER-SUPPLY
VOLTAGE
(V)
VCC
SUPPLY
VOLTAGE
(V)
COMPATIBILITY
3.3
Compatible with all CMOS
families.
5
Compatible with all TTL and
CMOS logic families.
5
3.3
Compatible with ACT and HCT
CMOS, and with TTL. ISL4221E,
ISL4223E and ISL3232E outputs
are incompatible with AC, HC,
and CD4000 CMOS inputs.
ISL3232E, ISL4221E, ISL4223E
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