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參數(shù)資料
| 型號： | ISL34341KIT1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL KIT FOR ISL34341 |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 1 |
| 系列： | * |
10
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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FN6827.1
October 8, 2010
micro-controller on each side of the of the link data can be
buffered and exchanged between the two. Up to 224 bytes
can be sent in each direction during each VSYNC active
period.
Master Mode
This is a mode activated by strapping the MASTER pin to a
‘1’ on the 34341 on the remote side of the controller. This is
a virtual extension of the I2C interface across the link that
allows the local processor to read and write slave devices
connected to the remote side I2C bus. No additional wires or
components are needed other than the serial link. The I2C
commands and data are transferred during video blanking
causing no interruptions in the video data. Data is
transported by the Side Channel across the link so the
maximum throughput would be the same.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure
you have the latest Rev.
DATE
REVISION
CHANGE
06/19/08
FN6827.1
Changed Tja and Tjc in Thermal Information from 33 and 4.5 to 40 and 12.
12/15/08
FN6827.0
Initial Release to web.
ISL34341
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