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參數(shù)資料
| 型號： | ISL34321INZ-T13 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SER/DESER LVDS SERDES 48TQFP |
| 產品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 1,000 |
| 功能： | 串行器/解串器 |
| 輸入類型： | LVTTL/LVCMOS |
| 輸出類型： | LVTTL，LVCMOS |
| 輸入數(shù)： | 2 |
| 輸出數(shù)： | 2 |
| 電源電壓： | 1.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應商設備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
ISL34321
10
FN6870.1
September 23, 2010
Power Supply Sequencing
The 3.3V supply must be higher than the 1.8V supply at
all times, including during power-up and power-down. To
meet this requirement, the 3.3V supply must be powered
up before the 1.8V supply.
For the deserializer, REF_CLK must not be applied before
the device is fully powered up. Applying REF_CLK before
power-up may require the deserializer to be manually
reset. A 10ms delay after the 1.8V supply is powered up
guarantees normal operation.
Power Supply Bypassing and Layout
The serializer and deserializer functions rely on the stable
functioning of PLLs locked to local reference sources or
locked to an incoming signal. It is important that the
various supplies (VDD_P, VDD_AN, VDD_CDR, VDD_TX)
be well bypassed over a wide range of frequencies, from
below the typical loop bandwidth of the PLL to
approaching the signal bit rate of the serial data. A
combination of different values of capacitors from
1000pF to 5F or more with low ESR characteristics is
generally required.
The parallel LVCMOS VDD_IO supply is inherently less
sensitive, but since the RGB and SYNC/DATAEN signals
can all swing on the same clock edge, the current in
these pins and the corresponding GND pins can undergo
substantial current flow changes, so once again, a
combination of different values of capacitors over a wide
range, with low ESR characteristics, is desirable.
A set of arrangements of this type is shown in Figure 4,
where each supply is bypassed with a ferrite-bead-based
choke, and a range of capacitors. A “choke” is preferable
to an “inductor” in this application, since a high-Q
inductor will be likely to cause one or more resonances
with the shunt capacitors, potentially causing problems
at or near those frequencies, while a “l(fā)ossy” choke will
reflect a high impedance over a wide frequency range.
The higher value capacitor, in particular, needs to be
chosen carefully, with special care regarding its ESR.
Very good results can be obtained with multilayer
ceramic capacitors, available from many suppliers, and
generally in small outlines (such as the 1210 outline
suggested in the schematic shown in Figure 4), which
provide good bypass capabilities down to a few mΩ at
1MHz to 2MHz. Other capacitor technologies may also be
suitable (perhaps niobium oxide), but “classic”
electrolytic capacitors frequently have ESR values of
above 1Ω, that nullify any decoupling effect above the
1kHz to 10kHz frequency range.
Capacitors of 0.1F offer low impedance in the 10MHz to
20MHz region, and 1000pF capacitors in the 100MHz to
200MHz region. In general, one of the lower value
capacitors should be used at each supply pin on the IC.
Figure 4 shows the grounding of the various capacitors to
the pin corresponding to the supply pin. Although all the
ground supplies are tied together, the PCB layout should
be arranged to emulate this arrangement, at least for the
smaller value (high frequency) capacitors, as much as
possible.
I2C Interface
The I2C interface allows access to internal registers used
to configure the SERDES and to obtain status
information. A serializer must be assigned a different
address than its deserializer counterpart. The upper 5
bits are permanently set to 011 11 and the lower 2bits
determined by pins as follows:
Thus, 16 SERDES can reside on the same bus. By
convention, when all address pins are tied low, the device
address is referred to as 0x78.
SCL and SDA are open drain to allow multiple devices to
share the bus. If not used, SCL and SDA should be tied to
VDD_IO.
Side Channel Interface
The Side Channel is a mechanism for transferring data
between the two chips on each end of the link. This data
is transferred during video blanking so none of the video
bandwidth is used. It has three basic uses:
Data exchanges between two processors
Master Mode I2C commands to remote slaves
Remote SERDES configuration
This interface allows the user to initialize registers,
control and monitor both SERDES chips from a single
micro controller which can reside on either side of the
serial link. This feature is used to automatically transport
the remote side serdes chip’s status back to a local
register. The Side Channel needs to be enabled (the
default) for this to work. In the case where there is a
micro controller on each side of the of the link, data can
be buffered and exchanged between the two. Up to 224
bytes can be sent in each direction during each VSYNC
active period.
01111
I2CA1 I2CA0
R/W
FIGURE 4. POWER SUPPLY BYPASSING
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