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參數(shù)資料
| 型號： | ISL28470EVAL1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 0K |
| 描述： | EVALUATION PLATFORM ISL28470 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 每 IC 通道數(shù)： | 4 - 四 |
| 放大器類型： | 儀表 |
| 輸出類型： | 單端，滿擺幅 |
| 轉(zhuǎn)換速率： | 0.5 V/µs |
| -3db帶寬： | 240kHz |
| 電流 - 輸出 / 通道： | 29mA |
| 工作溫度： | -40°C ~ 125°C |
| 電流供應(yīng)（主 IC）： | 260µA |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 5.5 V，±1.2 V ~ 2.75 V |
| 板類型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL28470 |
15
FN6260.6
October 21, 2009
range of input. See Input Bias Current vs Common-Mode
Input Voltage on page 8.
Input Bias Cancellation/Compensation
All three parts have an Input Bias Cancellation/Compensation
Circuit for both the input and feedback terminals (IN+, IN-, FB+
and FB-), achieving a low input bias current throughout the
input common-mode range and the operating temperature
range. While the PNP bipolar input stages are biased with an
adequate amount of biasing current for speed and increased
noise performance, the Input Bias Cancellation/Compensation
Circuit sinks most of the base current of the input transistors
leaving a small portion as input bias current, typically 500pA. In
addition, the Input Bias Cancellation/Compensation Circuit
maintains a smooth and flat behavior of input bias current over
the common mode range and over the operating temperature
range. The Input Bias Cancellation/Compensation Circuit
operates from input voltages of 10mV above the negative
supply to input voltages slightly above the positive supply. See
Input Bias Current vs Common-Mode Input Voltage in the
“Typical Performance Curves” on page 8.
Output Stage and Output Voltage Range
A Class AB common-source output stage drives the output.
The pair of complementary MOSFET devices drive the
output VOUT to within a few millivolts of the supply rails. At a
100k
Ω load, the PMOS sources current and pulls the output
up to 4mV below the positive supply. The NMOS sinks
current and pulls the output down to 4mV above the negative
supply, or ground in the case of a single supply operation.
The current sinking and sourcing capability are internally
limited to 29mA. When disabled, the outputs are in a high
impedance state.
Gain Setting
VIN, the potential difference across IN+ and IN-, is replicated
(less the input offset voltage) across FB+ and FB-. The
function of the in-amp is to maintain the differential voltage
across FB- and FB+ equal to IN+ and IN-; (FB- - FB+) =
(IN+ - IN-). Consequently, the transfer function can be
derived. The in-amp gain is set by two external resistors, the
feedback resistor RF, and the gain resistor RG.
connected to GND. With this configuration, Equation 1 is
only true for a positive swing in VIN; negative input swings
will be ignored because the output will be at ground.
Reference Connection
Unlike a 3 op amp in-amp realization, a finite series
resistance seen at the REF terminal does not degrade the
high CMRR performance, eliminating the need for an
additional external buffer amplifier. Figure 50 uses the FB+
pin to provide a high impedance REF terminal.
The FB+ pin is used as a REF terminal to center or to adjust
the output. Because the FB+ pin is a high impedance input,
an economical resistor divider can be used to set the voltage
at the REF terminal without degrading or affecting the CMRR
performance. Any voltage applied to the REF terminal will
shift VOUT by VREF times the closed loop gain, which is set
by resistors RF and RG. Note that any noise or unwanted
signals on the reference supply will be amplified at the
The FB+ pin can also be connected to the other end of
VOUT
1
R
F
R
G
--------
+
VIN
=
VIN
IN+
IN-
–
=
(EQ. 1)
+
-
+
-
IN+
IN-
FB+
FB-
V+
V-
2.4V TO 5.5V
RF
RG
VOUT
VCM
IN+
IN-
FIGURE 49. GAIN IS SET BY TWO EXTERNAL RESISTORS,
RF AND RG
(ISL28270, ISL28470)
FIGURE 50. GAIN SETTING AND REFERENCE CONNECTION
+
-
+
-
IN+
IN-
FB+
FB-
V+
V-
2.4V TO 5.5V
RF
RG
VOUT
VCM
IN+
IN-
REF
2.9V to 5.5V
R1
R2
(ISL28270, ISL28470)
VIN
IN+
IN-
–
=
(EQ. 2)
VOUT
1
R
F
R
G
--------
+
VIN
()
1
R
F
R
G
--------
+
VREF
()
+
=
ISL28270, ISL28273, ISL28470
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