20 November 30, 2012 FN6632.10 In applications where one or both amplifier input terminals are at risk of exposure" />
參數(shù)資料
型號(hào)： ISL28417FVZ-T7
廠商： Intersil
文件頁數(shù)： 13/34頁
文件大?。?/td> 0K
描述： IC OPAMP 1.5MHZ QUAD LP 14TSSOP
標(biāo)準(zhǔn)包裝： 1,000
放大器類型： 通用
電路數(shù)： 4
轉(zhuǎn)換速率： 0.5 V/µs
增益帶寬積： 1.5MHz
電流 - 輸入偏壓： 80pA
電壓 - 輸入偏移： 10µV
電流 - 電源： 440µA
電流 - 輸出 / 通道： 43mA
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 40 V，±2.25 V ~ 20 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
ISL28117, ISL28217, ISL28417
20
November 30, 2012
FN6632.10
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to
20mA max.
Output Current Limiting
The output current is internally limited to approximately ±45mA
at +25°C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the dual op amp. Continuous
operation under these conditions may degrade long term
reliability. Figures 27 and 28 show the current limit variation with
temperature.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28117, ISL28217 and ISL28417 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
Unused Channels
The ISL28217 is a dual op-amp. If the application only requires
one channel, the user must configure the unused channel to
prevent it from oscillating. The unused channel oscillates if the
input and output pins are floating. This results in higher than
expected supply currents and possible noise injection into the
channel being used. The proper way to prevent this oscillation is
to short the output to the inverting input and ground the positive
input, as shown in Figure 55.
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated using Equation 2:
where:
TMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Total supply voltage
IqMAX = Maximum quiescent supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
ISL28117, ISL28217 and ISL28417 SPICE
Model
Figure 56 shows the SPICE model schematic and Figure 57
shows the net list for the ISL28117, ISL28217 and ISL28417
SPICE model for a Grade “B” part. The model is a simplified
version of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC
parameters are VOS, IOS, total supply current and output voltage
swing. The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 6. The AVOL is adjusted
for 155dB with the dominate pole at 0.02Hz. The CMRR is set
(210dB, fcm = 10Hz). The input stage models the actual device to
present an accurate AC representation. The model is configured
for ambient temperature of +25°C.
Figures 58 through 68 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Closed Loop Gain vs RL, Large Signal Step Response, Open Loop
Gain Phase and Simulated CMRR vs Frequency.
FIGURE 55. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
TJMAX
TMAX θJAxPDMAXTOTAL
+
=
(EQ. 1)
PDMAX
VS IqMAX VS
(
- VOUTMAX)
VOUTMAX
RL
------------------------
×
+
×
=
(EQ. 2)
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