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| 型號： | ISL28278FAZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP DUAL RRIO PREC 16-QSOP |
| 標準包裝： | 97 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.14 V/µs |
| 增益帶寬積： | 300kHz |
| 電流 - 輸入偏壓： | 10pA |
| 電壓 - 輸入偏移： | 0.2µV |
| 電流 - 電源： | 120µA |
| 電流 - 輸出 / 通道： | 31mA |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 5.5 V，±1.2 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1235 (CN2011-ZH PDF) |
ISL28278, ISL28478
12
FN6145.4
August 16, 2011
Applications Information
The ISL28278 and ISL28478 are dual and quad CMOS rail-to-rail
input, output (RRIO) micropower operational amplifiers. These
devices are designed to operate from a single supply (2.4V to
5.5V) or dual supplies (±1.2V to ±2.75V) while drawing only
120A (ISL28278) of supply current. This combination of low
power and precision performance makes these devices suitable
for solar and battery power applications.
Rail-to-Rail Input
Many rail-to-rail input stages use two differential input pairs: a
long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties
have to be paid for this circuit topology. As the input signal moves
from one supply rail to another, the operational amplifier
switches from one input pair to the other, causing drastic
changes in input offset voltage and an undesired change in
magnitude and polarity of input offset current.
The ISL28278 achieves input rail-to-rail without sacrificing
important precision specifications and degrading distortion
performance. The input offset voltage exhibits smooth behavior
throughout the entire common-mode input range. The input bias
current versus the common-mode voltage range has undistorted
behavior typically from 100mV below the negative rail and 10%
higher than the V+ rail (0.5V higher than V+ when V+ equals 5V).
Input Protection
All input terminals have internal ESD protection diodes to the
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. There is an additional
pair of back-to-back diodes across the input terminals. For
applications in which the input differential voltage is expected to
exceed 0.5V, external series resistors must be used to ensure the
input currents never exceed 5mA (as shown in Figure 39).
Rail-to-Rail Output
A pair of complementary MOSFET devices are used to achieve the
rail-to-rail output swing. The NMOS sinks current to swing the output
in the negative direction. The PMOS sources current to swing the
output in the positive direction. Both parts, with a 100k
Ω load,
typically swing to within 4mV of the positive supply rail and within
3mV of the negative supply rail.
Enable/Disable Feature
The ISL28278 offers two EN pins (EN_A and EN_B) which disable
the op amp when pulled up to at least 2.0V. In the disabled state
(output in a high impedance state), the part typically consumes
4A. By disabling the part, multiple parts can be connected
together as a MUX. The outputs are tied together in parallel, and
a channel can be selected by the EN pins. The loading effects of
the feedback resistors of the disabled amplifier must be
considered when multiple amplifier outputs are connected
together. The EN pin also has an internal pull-down. If left open,
the EN pin pulls to the negative rail, and the device is enabled by
default.
Using Only One Channel
The ISL28278 and ISL28478 are dual and quad channel
op amps. If the application requires only one channel when using
the ISL28278 or fewer than four channels when using the
ISL28478, the user must configure any unused channels to
prevent them from oscillating. Unused channels oscillate if the
input and output pins are floating, resulting in higher than
FIGURE 38. -SLEW RATE vs TEMPERATURE, VOUT = ±1.5V, AV = +2
Typical Performance Curves V
+ = 5V, V
- = 0V, VCM = 2.5V, RL = Open, unless otherwise specified. (Continued)
-SLEW
RATE
(V/
s)
0.10
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.20
MAX
MIN
N = 1000
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
MEDIAN
FIGURE 39. INPUT ESD DIODE CURRENT LIMITING - UNITY GAIN
-
+
RIN
RL
VIN
VOUT
V+
V-
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