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參數(shù)資料
| 型號： | ISL28271FAZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INSTR AMP RRIO DUAL 16-QSOP |
| 標準包裝： | 1 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.5 V/µs |
| -3db帶寬： | 180kHz |
| 電流 - 輸入偏壓： | 10pA |
| 電壓 - 輸入偏移： | 35µV |
| 電流 - 電源： | 120µA |
| 電流 - 輸出 / 通道： | 31mA |
| 電壓 - 電源，單路/雙路(±)： | 2.4 V ~ 5.5 V，±1.2 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1234 (CN2011-ZH PDF) |
| 其它名稱： | ISL28271FAZ-T7DKR |
12
FN6390.2
August 17, 2007
.
The FB+ pin is used as a REF terminal to center or to adjust
the output. Because the FB+ pin is a high impedance input,
an economical resistor divider can be used to set the voltage
at the REF terminal without degrading or affecting the CMRR
performance. Any voltage applied to the REF terminal will
shift VOUT by VREF times the closed loop gain, which is set
The FB+ pin can also be connected to the other end of
the in-amp maintains constant differential voltage across the
input terminals and feedback terminals (FB- - FB+) =
(IN+ - IN-), the transfer function of Figure 39 can be derived.
A finite resistance RS in series with the VREF source, adds
an output offset of VIN*(RS/RG). As the series resistance RS
Figure 39. VOUT is simply shifted by an amount VREF.
External Resistor Mismatches
Because of the independent pair of feedback terminals
provided by the in-amps, the CMRR is not degraded by any
resistor mismatches. Hence, unlike a three op amp and
especially a two op amp in-amp realization, the ISL28271
and ISL28272 reduce the cost of external components by
allowing the use of 1% or more tolerance resistors without
sacrificing CMRR performance. The CMRR will be typically
110dB regardless of the tolerance of the resistors used.
Instead, a resistor mismatch results in a higher deviation
from the theoretical gain - Gain Error.
Gain Error and Accuracy
The gain error indicated in the “Electrical Specifications”
table on page 2 is the inherent gain error alone. The gain
error specification listed does not include the gain error
contributed by the resistors. There is an additional gain error
due to the tolerance of the resistors used. The resulting non-
ideal transfer function effectively becomes:
Where:
ERG = Tolerance of RG
ERF = Tolerance of RF
EG = Gain Error of the ISL28271
The term [1 - (ERG +ERF +EG)] is the deviation from the
theoretical gain. Thus, (ERG +ERF +EG) is the total gain
error. For example, if 1% resistors are used, the total gain
error would be:
Disable/Power-Down
The ISL28271 and ISL28272 have an enable/disable pin for
each channel. They can be powered down to reduce the
supply current to typically 4A when all channels are off.
When disabled, the corresponding output is in a high
impedance state. The active low EN pin has an internal pull
down and hence can be left floating and the in-amp enabled
by default. When the EN is connected to an external logic,
the in-amp will shutdown when EN pin is pulled above 2V,
and will power up when EN bar is pulled below 0.8V.
FIGURE 38. GAIN SETTING AND REFERENCE CONNECTION
+
-
+
-
IN+
IN-
FB+
FB-
V+
V-
EN
2.4V TO 5.5V
RF
RG
VOUT
EN
ISL28271
VCM
IN+
IN-
REF
2.9V to 5.5V
R1
R2
ISL28271
ISL28272
VIN
IN+
IN-
–
=
(EQ. 2)
VOUT
1
R
F
R
G
--------
+
VIN
()
1
R
F
R
G
--------
+
VREF
()
+
=
FIGURE 39. REFERENCE CONNECTION WITH AN AVAILABLE
VREF
+
-
+
-
IN+
IN-
FB+
FB-
V+
V-
EN
2.4V TO 5.5V
RF
RG
VOUT
EN
ISL28271
VCM
IN+
IN-
VREF
RS
ISL28271
ISL28272
VIN
IN+
IN-
–
=
(EQ. 3)
VOUT
1
R
S
R
F
+
R
G
----------------------
+
VREF
+
=
(EQ. 4)
VOUT
1
R
F
R
G
--------
+
VIN
()
VREF
()
+
=
VOUT
1
R
F
R
G
--------
+
1E
RG
E
RF
E
G
++
()
±
[] VIN
×
=
(EQ. 5)
TotalGainError
E
RG
E
RF
E
G typical
()
++
()
±
=
TotalGainError
0.01
0.005
++
()
2.5%
±
=
±
=
ISL28271, ISL28272
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