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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ISL28133EVAL1Z |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/20闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | EVAL BOARD FOR ISL28133 SOT23-5 |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Patient Monitoring and Diagnostic Equipment Solutions Solutions for Industrial Control Applications |
| 妯欐簴鍖呰锛� | 1 |
| 姣� IC 閫氶亾鏁�(sh霉)锛� | 1 - 鍠� |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | 鏂疯矾鍣紙闆舵紓绉伙級 |
| 杓稿嚭椤炲瀷锛� | 鍠锛屾豢鎿哄箙 |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 0.2 V/µs |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 26mA |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 闆绘祦渚涙噳(y墨ng)锛堜富 IC锛夛細 | 18µA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 2.4 V ~ 5.5 V锛�±1.2 V ~ 2.75 V |
| 鏉块鍨嬶細 | 瀹屽叏濉厖 |
| 宸蹭緵鐗╁搧锛� | 鏉� |
| 宸茬敤 IC / 闆朵欢锛� | ISL28133 |
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ISL28133
11
FN6560.6
February 19, 2014
Applications Information
Functional Description
The ISL28133 uses a proprietary chopper-stabilized architecture
shown in the 鈥淏lock Diagram鈥� on page 2. The ISL28133
combines a 400kHz main amplifier with a very high open loop
gain (174dB) chopper stabilized amplifier to achieve very low
offset voltage and drift (2V, 0.02V/掳C typical) while
consuming only 18A of supply current per channel.
This multi-path amplifier architecture contains a time continuous
main amplifier whose input DC offset is corrected by a
parallel-connected, high gain chopper stabilized DC correction
amplifier operating at 100kHz. From DC to ~5kHz, both
amplifiers are active with DC offset correction and most of the
low frequency gain is provided by the chopper amplifier. A 5kHz
crossover filter cuts off the low frequency amplifier path leaving
the main amplifier active out to the 400kHz gain-bandwidth
product of the device.
The key benefits of this architecture for precision applications are
very high open loop gain, very low DC offset, and low 1/f noise.
The noise is virtually flat across the frequency range from a few
mHz out to 100kHz, except for the narrow noise peak at the
amplifier crossover frequency (5kHz).
Rail-to-rail Input and Output (RRIO)
The RRIO CMOS amplifier uses parallel input PMOS and NMOS
that enable the inputs to swing 100mV beyond either supply rail.
The inverting and non-inverting inputs do not have back-to-back
input clamp diodes and are capable of maintaining high input
impedance at high differential input voltages. This is effective in
eliminating output distortion caused by high slew-rate input
signals.
The output stage uses common source connected PMOS and
NMOS devices to achieve rail-to-rail output drive capability with
17mA current limit and the capability to swing to within 20mV of
either rail while driving a 10k
惟 load.
IN+ and IN- Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. For applications where
either input is expected to exceed the rails by 0.5V, an external
series resistor must be used to ensure the input currents never
exceed 20mA (see Figure 35).
Layout Guidelines for High Impedance Inputs
To achieve the maximum performance of the high input
impedance and low offset voltage of the ISL28133 amplifiers,
care should be taken in the circuit board layout. The PC board
surface must remain clean and free of moisture to avoid leakage
currents between adjacent traces. Surface coating of the circuit
board will reduce surface moisture and provide a humidity barrier,
reducing parasitic resistance on the board.
High Gain, Precision DC-Coupled Amplifier
The circuit in Figure 36 implements a single-stage, 10kV/V
DC-coupled amplifier with an input DC sensitivity of under 100nV
that is only possible using a low VOS amplifier with high open
loop gain. This circuit is practical down to 1.8V due to it's
rail-to-rail input and output capability. Standard high gain DC
amplifiers operating from low voltage supplies are not practical
at these high gains using typical low offset precision op amps
because the input offset voltage and temperature coefficient
consume most of the available output voltage swing. For
example, a typical precision amplifier in a gain of 10kV/V with a
卤100V VOS and a temperature coefficient of 0.5V/掳C would
produce a DC error at the output of >1V with an additional
5mV掳C of temperature dependent error. At 3V, this DC error
consumes > 30% of the total supply voltage, making it
impractical to measure sub-microvolt low frequency signals.
The 卤8V max VOS and 0.075V/掳C of the ISL28133 produces a
temperature stable maximum DC output error of only 卤80mV
with a maximum temperature drift of 0.75mV/掳C. The additional
benefit of a very low 1/f noise corner frequency and some
feedback filtering enables DC voltages and voltage fluctuations
well below 100nV to be easily detected with a simple single
stage amplifier.
FIGURE 35. INPUT CURRENT LIMITING
-
+
RIN
RL
VIN
VOUT
FIGURE 36. HIGH GAIN, PRECISION DC-COUPLED AMPLIFIER
-
+
100
RL
VIN
VOUT
1M
100
-2.5V
+2.5V
ACL = 10kV/V
CF
0.018F
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| MIC2045-1YTS TR | IC DISTRIBUTION SW SGL 16-TSSOP |
| VI-J7T-EY | CONVERTER MOD DC/DC 6.5V 50W |
| 202D963-3-0 | BOOT MOLDED |
| 202A174-25-0 | BOOT MOLDED |
| 202A174-4-0 | BOOT MOLDED |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ISL28133FEZ | 鍒堕€犲晢:Intersil 鍔熻兘鎻忚堪:Single Micropower, Chopper Stabilized, RRIO Operational Amplifier |
| ISL28133FEZ-T7 | 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28133FEZ SINGLE MICROPWR ZERO-DRIFT RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V |
| ISL28133FEZ-T7A | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Single, Dual, and Quad Micropower, Zero-Drift, RRIO Operational Amplifiers |
| ISL28133FHZ | 鍒堕€犲晢:Intersil 鍔熻兘鎻忚堪:Single Micropower, Chopper Stabilized, RRIO Operational Amplifier |
| ISL28133FHZ-T7 | 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28133FHZ MICROPWR PRCSN 5V CMOS OPER RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V |
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