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| 型號(hào)： | ISL26134AVZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 7/23頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT SRL 80SPS 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 80 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)差分，雙極 |
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ISL26132, ISL26134
15
FN6954.1
September 9, 2011
Conversion Data Rate
The SPEED pin is used to select between the 10Sps and 80Sps
conversion rates. The 10Sps rate (SPEED = Low) is preferred in
applications requiring 50/60Hz noise rejection. Note that the
sample rate is directly related to the oscillator frequency, as
491,520 clocks are required to perform a conversion at the
10Sps rate, and 61,440 clocks at the 80Sps rate.
Output Data Format
The 24-bit converter output word is delivered in two’s
complement format. Input exceeding full scale results in a
clipped output which will not return to in-range values until after
the input signal has returned to the specified allowable voltage
range and the digital filter has settled as discussed previously.
Reading Conversion Data from the Serial
Data Output/Ready SDO/RDY Pin
When the ADC is powered, it will automatically begin doing
conversions. The SDO/RDY signal will go low to indicate the
completion of a conversion. After the SDO/RDY signal goes low,
the MSB data bit of the conversion word will be output from the
SDO/RDY pin after SCLK is transitioned from a low to a high.
Each subsequent new data bit is also output on the rising edge of
SCLK (see Figure 30). The receiving device should use the falling
edge of SCLK to latch the data bits. After the 24th SCLK, the
SDO/RDY output will remain in the state of the LSB data bit until
a new conversion is completed. At this time, the SDO/RDY will go
high if low and then go low to indicate that a new conversion
word is available. If not all data bits are read from the SDO/RDY
pin prior to the completion of a new conversion, they will be
overwritten. SCLK should be low during time t6, as shown in
Figure 30, when SDO/RDY is high.
If the user wants the SDO/RDY signal to go high after reading the
24 bits of the conversion data word, a 25th SCLK can be issued.
The 25th SCLK will force the SDO/RDY signal to go high and
remain high until it falls to signal that a new conversion word is
available. Figure 31 illustrates the behavior of the SDO/RDY
signal when a 25th SCLK is used.
FIGURE 29. SDO/RDY DELAY AFTER MULTIPLEXER CHANGE
SDO/RDY
TABLE 9. OUTPUT CODES CORRESPONDING TO INPUT
INPUT SIGNAL
OUTPUT CODE (HEX)
≥ + 0.5VREF/GAIN
7FFFFF
(+0.5VREF/GAIN)/(223 - 1)
000001
0
000000
(-0.5VREF/GAIN)/(223 - 1)
FFFFFF
≤ - 0.5VREF/GAIN
800000
FIGURE 30. OUTPUT DATA WAVEFORMS USING 24 SCLKS TO READ CONVERSION DATA
SDO/RDY
DATA READY
DATA
MSB
LSB
NEW DATA READY
23
22
21
0
SCLK
t4
t2
1
t3
24
t5
t6
t3
t7
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