2 FN7586.1 December 9, 2010 Block Diagram Pin Configuration ISL24201 (8 LD TDFN) TOP VIEW FIGURE 2. BLOCK DIAGRAM OF THE ISL24201 GND " />
參數(shù)資料
型號: ISL24201IRTZ
廠商: Intersil
文件頁數(shù): 5/12頁
文件大小: 0K
描述: IC VCOM CALIBRATOR I2C 8TDFN
標準包裝: 100
類型: 校準器
應用: LCD 顯示器
安裝類型: 表面貼裝
封裝/外殼: 8-WSDFN 裸露焊盤
供應商設備封裝: 8-TDFN(3x3)
包裝: 管件
ISL24201
2
FN7586.1
December 9, 2010
Block Diagram
Pin Configuration
ISL24201
(8 LD TDFN)
TOP VIEW
FIGURE 2. BLOCK DIAGRAM OF THE ISL24201
GND
I2C
INTERFACE
DAC
REGISTERS
ANALOG DCP
AND
CURRENT SINK
8-BIT EEPROM
SCL
SDA
WP
VDD
AVDD
OUT
SET
1
8
2
5
7
6
3
4
ISL24201
CURRENT
SINK
Q1
A1
OUT
AVDD
WP
GND
1
2
3
4
8
7
6
5
SET
SCL
SDA
VDD
PAD
(THERMAL PAD CONNECTS TO GND)
Pin Descriptions
PIN
NAME
PIN
NUMBER
FUNCTION
OUT
1
Adjustable Sink Current Output Pin. The current
sunk into the OUT pin is equal to the DAC setting
times the maximum adjustable sink current
divided by 256. See the “SET” pin function
description below (pin 8) for the maximum
adjustable sink current setting.
AVDD
2
High-Voltage Analog Supply. Bypass to GND
with 0.1F capacitor.
WP
3
EEPROM Write Protect. Active Low.
0 = Programming disabled;
1 = Programming allowed. This pin has an
internal pull-down current sink
GND
4
Ground connection.
VDD
5
System power supply input. Bypass to GND
with 0.1F capacitor.
SDA
6
I2C Serial Data Input and Output
SCL
7
I2C Clock Input
SET
8
Maximum Sink Current Adjustment Point.
Connect a resistor from SET to GND to set the
maximum adjustable sink current of the OUT
pin. The maximum adjustable sink current is
equal to (AVDD/20) divided by RSET.
PAD
-
Thermal pad should be connected to system
ground plane to optimize thermal performance.
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