17 Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the qualit" />
參數(shù)資料
型號: ISL23348UFRZ-TK
廠商: Intersil
文件頁數(shù): 9/19頁
文件大?。?/td> 0K
描述: IC DGTL POT 4CH 50K 20QFN
標(biāo)準包裝: 1,000
系列: XDCP™
接片: 128
電阻(歐姆): 50k
電路數(shù): 4
溫度系數(shù): 標(biāo)準值 65 ppm/°C
存儲器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 1.2 V ~ 5.5 V,1.7 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 20-QFN(3x4)
包裝: 帶卷 (TR)
ISL23348
17
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7903.1
August 24, 2011
For additional products, see www.intersil.com/product_tree
Applications Information
VLOGIC Requirements
VLOGIC should be powered continuously during normal operation.
In a case where turning VLOGIC OFF is necessary, it is
recommended to ground the VLOGIC pin of the ISL23348.
Grounding the VLOGIC pin or both VLOGIC and VCC does not affect
other devices on the same bus. It is good practice to put a 1F
cap in parallel to 0.1F as close to the VLOGIC pin as possible.
VCC Requirements and Placement
It is recommended to put a 1F capacitor in parallel with 0.1F
decoupling capacitor close to the VCC pin.
Wiper Transition
When stepping up through each tap in voltage divider mode,
some tap transition points can result in noticeable voltage
transients, or overshoot/undershoot, resulting from the sudden
transition from a very low impedance “make” to a much higher
impedance “break” within a short period of time (<1s). There
are several code transitions such as 0Fh to 10h, 1Fh to 20h,
which have higher transient glitch. Note, that all switching
transients will settle well within the settling time as stated in the
datasheet. A small capacitor can be added externally to reduce
the amplitude of these voltage transients. However, that will also
reduce the useful bandwidth of the circuit, thus may not be a
good solution for some applications. It may be a good idea, in
that case, to use fast amplifiers in a signal chain for fast
recovery.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address
some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product
families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil
product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL23348
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
DATE
REVISION
CHANGE
August 24, 2011
FN7903.1
Page 1 - Replace Figure 1 with Figure 1 from ISL23448
Corrected limits in Analog Spec table for INL, DNL, FSerror, ZSerror, RINL, RDNL, Roffset.
August 19, 2011
FN7903.0
Initial release.
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